Past Questions — 2010

A band-stop filter (also known as a notch filter or band-rejection filter) is a type of filter that allows most frequencies to pass through while blocking (attenuating) a specific range of frequencies. 1. **Analysis of Option (a):** This is the definition of a band-stop filter. It has two cutoff frequencies, f1 (lower) and f2 (upper). Frequencies below f1 and above f2 are passed, while frequencies between f1 and f2 are attenuated. This is correct. 2. **Analysis of Option (b):** A filter that attenuates all frequencies less than a certain cutoff frequency is called a High-Pass Filter (HPF). 3. **Analysis of Option (c):** A filter that attenuates all frequencies above a certain cutoff frequency is called a Low-Pass Filter (LPF). 4. **Analysis of Option (d):** A filter that passes only frequencies between two cutoff frequencies and attenuates everything else is called a Band-Pass Filter (BPF).

In filter theory, a filter is designed to allow certain frequencies to pass through while blocking others. 1. **Pass Band**: This is the range of frequencies that the filter is intended to allow to pass with minimum loss. In an 'ideal' filter, there should be absolutely no loss of signal strength in this region. Attenuation refers to the reduction in signal strength; therefore, an ideal filter must have zero attenuation in the pass band. 2. **Stop Band (Attenuation Band)**: This is the range of frequencies that the filter is intended to block. In an ideal filter, the attenuation in this band should be infinite (meaning the signal is completely blocked). Evaluating the options: - Option (a) is incorrect because the attenuation band is where we want maximum attenuation, not zero. - Option (b) is correct because an ideal filter allows signals in the pass band to pass without any loss (zero attenuation). - Option (c) is incorrect because infinite attenuation in the pass band would mean the filter blocks the very signals it is designed to let through. - Option (d) is incorrect as option (b) is the correct technical definition.

A Half Adder is a combinational circuit used to add two single-bit binary numbers (A and B). It has two outputs: the Sum (S) and the Carry (C). 1. The Sum (S) is the result of the addition of the two bits. According to the truth table for binary addition: - 0 + 0 = 0 - 0 + 1 = 1 - 1 + 0 = 1 - 1 + 1 = 0 (with a carry of 1) This logic corresponds exactly to the Exclusive-OR (EX-OR) gate, where the output is high only when the inputs are different. Therefore, Sum = A ⊕ B. 2. The Carry (C) is generated only when both inputs are 1 (1 + 1 = 10 in binary). This logic corresponds to the AND gate. Therefore, Carry = A · B. Since the question asks for the output of the EX-OR gate in a half adder, the correct answer is the Sum.

A linear network is defined by the property of linearity, which consists of two main principles: Homogeneity (Scaling) and Superposition. 1. Homogeneity Principle: If an input x(t) produces an output y(t), then a scaled input αx(t) will produce a scaled output αy(t). 2. In this specific problem, the input is 'tripled', meaning the scaling factor α = 3. 3. According to the property of linearity, if the input is multiplied by 3, the output must also be multiplied by 3 (tripled). Evaluating the options: - Option (a) 'reduced to one-third' is incorrect as it describes an inverse relationship. - Option (b) 'doubled' is incorrect as the scaling factor is 3, not 2. - Option (c) 'halved' is incorrect as it describes a reduction. Since the correct result (tripled) is not listed among options a, b, or c, the correct choice is 'none of these'.

To solve this question, we must analyze the behavior of impedance (Z) and admittance (Y) at resonance for both series and parallel circuits. 1. **Series Resonance:** At resonance, the inductive reactance (XL) and capacitive reactance (XC) cancel each other out (XL = XC). The total impedance Z = R + j(XL - XC) becomes Z = R. Since the reactive components cancel, the impedance is at its **minimum** value. Consequently, the admittance (Y = 1/Z) is at its **maximum** value. 2. **Parallel Resonance:** In an ideal parallel resonant circuit, the inductive and capacitive branches cancel each other's currents. This results in the total impedance Z reaching its **maximum** value (ideally infinite in a lossless circuit). Consequently, the admittance (Y = 1/Z) is at its **minimum** value. **Analysis of Options:** - Option (a) 'maximum' is only true for impedance in parallel resonance. - Option (b) 'minimum' is only true for impedance in series resonance. - Option (c) is technically incorrect as resonance represents extreme values (min/max), not medium values. Because the question asks for the impedance and admittance of *both* series and parallel circuits simultaneously, and the behaviors are opposite (Series: Z min, Y max; Parallel: Z max, Y min), no single option (a, b, or c) correctly describes both scenarios. Therefore, the correct choice is 'None of these'.

A Full Adder is a combinational circuit used in digital electronics to perform the addition of three binary digits (bits). Specifically, it adds two significant bits (A and B) and a carry bit (Cin) generated from a previous less-significant stage. 1. Input Analysis: A full adder has three inputs: Input A, Input B, and Carry-in (Cin). 2. Output Analysis: It produces two outputs: Sum (S) and Carry-out (Cout). 3. Comparison with Half Adder: A Half Adder can only add 2 bits (A and B) and cannot handle a carry from a previous stage. To handle the carry, a Full Adder is required, which effectively adds 3 bits at a time. Therefore, the correct number of digits added by a full adder circuit is 3.

In a parallel RLC circuit, the differential equation governing the voltage across the components leads to a characteristic equation. For an underdamped response, the solution is a decaying sinusoid. The general form of the voltage response is v(t) = V_max * e^(-αt) * sin(ωd t + φ), where α is the damping coefficient. For a parallel RLC network, the damping coefficient α is given by α = 1 / (2RC). The time constant (τ) of the exponential decay is the reciprocal of the damping coefficient: τ = 1 / α. Therefore, τ = 1 / (1 / 2RC) = 2RC. Analysis of options: - Option (a) 1/(2RC) is the damping coefficient (α), not the time constant (τ). - Option (b) 2RC is the correct time constant for a parallel RLC circuit. - Option (c) 1/LC is related to the square of the undamped natural frequency (ω0² = 1/LC). - Option (d) L/C is related to the square of the time constant for a series RLC circuit (where τ = 2L/R).

In the two-wattmeter method for measuring power in a balanced three-phase system, the readings of the two wattmeters (W1 and W2) are given by: W1 = V_L I_L cos(30° + φ) W2 = V_L I_L cos(30° - φ) where φ is the phase angle of the load. Given the ratio W1 : W2 = 1 : 2, we have: (cos(30° + φ)) / (cos(30° - φ)) = 1 / 2 Using the trigonometric identity cos(A ± B) = cos A cos B ∓ sin A sin B: [cos 30° cos φ - sin 30° sin φ] / [cos 30° cos φ + sin 30° sin φ] = 1 / 2 Substituting the values cos 30° = √3/2 and sin 30° = 1/2: [(√3/2) cos φ - (1/2) sin φ] / [(√3/2) cos φ + (1/2) sin φ] = 1 / 2 Cross-multiplying: 2[(√3/2) cos φ - (1/2) sin φ] = (√3/2) cos φ + (1/2) sin φ √3 cos φ - sin φ = (√3/2) cos φ + (1/2) sin φ Rearranging the terms to group cos φ and sin φ: √3 cos φ - (√3/2) cos φ = sin φ + (1/2) sin φ (√3/2) cos φ = (3/2) sin φ Solving for tan φ: tan φ = (√3/2) / (3/2) = √3 / 3 = 1 / √3 Since tan φ = 1/√3, the phase angle φ = 30°. The power factor (pf) is defined as cos φ: pf = cos(30°) = √3/2 Therefore, the circuit power factor is √3/2.

In network theory and system analysis, the 'input' refers to the external signal or energy source applied to a system to produce a result. This input is technically referred to as the 'stimulus' or the 'excitation'. 1. Stimulus: This is a general term used in systems theory to describe the external influence that triggers a reaction from the system. 2. Excitation: In electrical engineering, this term specifically refers to the application of a voltage or current source to a network to 'excite' the components and create a measurable output. 3. Response: This is the 'output' of the network (e.g., the resulting current or voltage) in reaction to the input. Therefore, option (c) is the opposite of the input. Since both 'stimulus' and 'excitation' are synonymous with 'input' in the context of network analysis, the correct choice is 'either (a) or (b)'.

Equal wattmeter readings imply tanφ=0, φ=0, power factor cosφ=1.

A substring is defined as a contiguous sequence of characters within a string. To determine the total number of substrings of a string of length n, we can count them based on their length: 1. Substrings of length 1: There are n such substrings (each individual character). 2. Substrings of length 2: There are (n - 1) such substrings. 3. Substrings of length 3: There are (n - 2) such substrings. ... n. Substrings of length n: There is 1 such substring (the string itself). The total number of substrings is the sum of this arithmetic progression: Total = n + (n - 1) + (n - 2) + ... + 1. Using the formula for the sum of the first n natural numbers, Sum = n(n + 1)/2. Alternatively, a substring is uniquely defined by its start position and end position. There are n choices for the start position and n choices for the end position, but since the start must be less than or equal to the end, this is equivalent to choosing 2 positions out of n+1 (the boundaries between characters) to define the substring: Combination(n+1, 2) = (n+1)! / (2! * (n-1)!) = (n+1)n / 2. Comparing this to the options: - Option a (n) only counts substrings of length 1. - Option b (n^2) is incorrect. - Option c (n(n-1)/2) counts substrings of length > 1 only (excluding single characters). - Option d (n(n+1)/2) is the correct mathematical derivation.

In network theory, 'steady-state condition' for a DC circuit refers to the state reached after a long period of time where the voltages and currents have stabilized (transients have decayed). 1. Inductor (L): The voltage across an inductor is given by V = L(di/dt). In DC steady state, the current (i) becomes constant, meaning the rate of change of current (di/dt) is zero. Therefore, V = 0. A component with zero voltage drop across it while carrying current behaves as a short circuit. 2. Capacitor (C): The current through a capacitor is given by I = C(dv/dt). In DC steady state, the voltage (v) across the capacitor becomes constant, meaning the rate of change of voltage (dv/dt) is zero. Therefore, I = 0. A component that allows no current to flow through it behaves as an open circuit. Thus, during DC steady-state, the inductor behaves as a short circuit and the capacitor behaves as an open circuit.

To determine if a relation is a partial ordering, it must satisfy three specific properties: reflexivity, anti-symmetry, and transitivity. 1. **Reflexivity**: A relation R on a set S is reflexive if for every element a in S, (a, a) is in R. For the 'less than' relation (<), it is required that a < a for all real numbers. However, no real number is less than itself (e.g., 5 < 5 is false). Therefore, the relation is **not reflexive** (it is actually irreflexive). 2. **Anti-symmetry**: A relation R is anti-symmetric if whenever (a, b) is in R and (b, a) is in R, then a = b. For the 'less than' relation, if a < b, it is impossible for b < a to be true simultaneously. While this vacuously satisfies the condition for anti-symmetry in some logical contexts, the primary failure of the 'less than' relation to be a partial order is its lack of reflexivity. 3. **Comparison with Partial Order**: A partial order is defined as a reflexive, anti-symmetric, and transitive relation. Since the 'less than' relation (<) is not reflexive, it cannot be a partial ordering. (Note: The 'less than or equal to' relation, ≤, is a partial ordering because it is reflexive). Evaluating the options: - Option (a) and (b) are incorrect because they claim it is a partial ordering. - Option (c) mentions 'asymmetric'. A relation is asymmetric if (a, b) implies NOT (b, a). The 'less than' relation IS asymmetric. Therefore, saying it is 'not asymmetric' is incorrect. - Option (d) correctly identifies that it is not a partial ordering. While the 'less than' relation is technically anti-symmetric (vacuously), in the context of standard multiple-choice questions for this exam, the lack of reflexivity is the definitive reason it fails to be a partial order. Option (d) is the most accurate choice among the provided options to disqualify it as a partial ordering.

Even-zero count: an=2*an-1 (end 1/2) + (3^{n-1}-an-1) (end 0 makes odd even) = an-1+3^{n-1}.

Thevenin's and Norton's theorems are used to simplify a linear, bilateral network into a single source and a single impedance. For these theorems to be applicable, the network must be 'self-contained'—meaning all sources and dependencies must exist within the network being simplified. 1. Options (a) and (b) are incorrect because Thevenin/Norton equivalents are specifically designed to handle independent voltage and current sources. 2. Option (c) is incorrect because dependent sources (controlled sources) located *within* the network can be handled using the test-source method (applying a voltage or current source at the terminals to find the equivalent resistance). 3. Option (d) is correct because if a source or a component within the network depends on a variable (voltage or current) located *outside* the network (in another network or the load), the network is no longer linear or independent. The equivalent circuit would change depending on what is connected to the terminals, violating the fundamental premise of Thevenin's theorem, which states that the equivalent circuit remains constant regardless of the load connected.

In discrete mathematics, there is a fundamental one-to-one correspondence between the number of equivalence relations on a set and the number of partitions of that set. The number of ways to partition a set of n elements is given by the Bell number, denoted as B_n. For a set with n = 4 elements {1, 2, 3, 4}, we can calculate the Bell numbers using the Bell triangle or the recurrence relation B_{n+1} = Σ (k=0 to n) [C(n, k) * B_k], where B_0 = 1. Step-by-step calculation: 1. B_0 = 1 2. B_1 = C(0,0) * B_0 = 1 * 1 = 1 3. B_2 = C(1,0)*B_0 + C(1,1)*B_1 = (1*1) + (1*1) = 2 4. B_3 = C(2,0)*B_0 + C(2,1)*B_1 + C(2,2)*B_2 = (1*1) + (2*1) + (1*2) = 1 + 2 + 2 = 5 5. B_4 = C(3,0)*B_0 + C(3,1)*B_1 + C(3,2)*B_2 + C(3,3)*B_3 = (1*1) + (3*1) + (3*2) + (1*5) = 1 + 3 + 6 + 5 = 15. Alternatively, we can list the partition types for n=4: - {4}: 1 way (all in one block) - {3, 1}: 4 ways (choosing 1 element to be alone) - {2, 2}: 3 ways (pairing elements: {12,34}, {13,24}, {14,23}) - {2, 1, 1}: 6 ways (choosing 2 elements to be together) - {1, 1, 1, 1}: 1 way (all elements separate) Total = 1 + 4 + 3 + 6 + 1 = 15. Therefore, the number of equivalence relations is 15.

A tautology is a proposition that is true under every possible assignment of truth values to its variables. Let's analyze the options using truth tables or logical equivalences: 1. Option (a): '(p ∨ q) →' is an incomplete expression (missing the consequent), so it cannot be a tautology. 2. Option (b): 'p ∨ (q → p)'. Using the implication identity (A → B ≡ ¬A ∨ B), this becomes 'p ∨ (¬q ∨ p)', which simplifies to 'p ∨ ¬q'. This is false when p is False and q is True. Thus, it is not a tautology. 3. Option (c): 'p ∨ (p → q)'. Using the implication identity, this becomes 'p ∨ (¬p ∨ q)'. By associative law, '(p ∨ ¬p) ∨ q'. Since (p ∨ ¬p) is always True (Law of Excluded Middle), the expression is 'True ∨ q', which is always True. Wait, let's re-verify: p ∨ (¬p ∨ q) = (p ∨ ¬p) ∨ q = T ∨ q = T. This is also a tautology. 4. Option (d): 'p → (q → p)'. Using the implication identity: ¬p ∨ (¬q ∨ p). By commutative and associative laws, this is (¬p ∨ p) ∨ ¬q. Since (¬p ∨ p) is always True, the expression is 'True ∨ ¬q', which is always True. This is a classic tautology known as the Law of Simplification in propositional logic. Comparing (c) and (d): In many standard textbooks for competitive exams, 'p → (q → p)' is the textbook example of a tautology. However, mathematically, both (c) and (d) evaluate to True. Looking at the structure of the question from the MPSC 2010 paper, option (d) is the standard logical axiom. Let's re-check (c): p ∨ (p → q) = p ∨ (¬p ∨ q) = (p ∨ ¬p) ∨ q = T ∨ q = T. Both are technically tautologies, but (d) is the most fundamental form of a tautology used in logic exams.

Context-Free Languages (CFLs), which are generated by Context-Free Grammars (CFGs), have specific closure properties. 1. **Union (Option b):** CFLs are closed under union. If L1 and L2 are CFLs, then L1 ∪ L2 is also a CFL. This is easily proven by creating a new start symbol S → S1 | S2. 2. **Kleene Star (Option d):** CFLs are closed under Kleene star. If L is a CFL, then L* is also a CFL. This is proven by adding a rule S → SS | ε. 3. **Product/Concatenation (Option a):** CFLs are closed under concatenation (product). If L1 and L2 are CFLs, then L1L2 is also a CFL. This is proven by adding a rule S → S1S2. 4. **Complementation (Option c):** CFLs are NOT closed under complementation. If L is a CFL, its complement (Σ* - L) is not necessarily a CFL. A classic example is the language L = {a^n b^n c^n | n ≥ 0}, which is not context-free, but its complement is context-free. Furthermore, since CFLs are closed under union but not under complementation, they cannot be closed under intersection (by De Morgan's Law: L1 ∩ L2 = Complement(Complement(L1) ∪ Complement(L2))). Therefore, complementation is the correct answer.

In a series RLC circuit, the total impedance (Z) is given by the formula Z = √[R² + (XL - XC)²], where R is resistance, XL is inductive reactance, and XC is capacitive reactance. Resonance occurs when the inductive reactance equals the capacitive reactance (XL = XC). At this specific frequency, the reactive components cancel each other out, making the circuit purely resistive (Z = R). In a purely resistive circuit, the phase angle (φ) between the total voltage and the total current is zero (cos φ = 1). Therefore, the current and voltage are in phase. Analysis of other options: - Option b: Opposite phase (180 degrees) does not occur in a standard passive series RLC circuit. - Option c: Current leads voltage when the circuit is capacitive (XC > XL), which happens below the resonant frequency. - Option d: Voltage leads current when the circuit is inductive (XL > XC), which happens above the resonant frequency.

A Context-Free Grammar (CFG) is in Chomsky Normal Form (CNF) if all its production rules are of the form: 1) A → BC (where B and C are non-terminals) or 2) A → a (where 'a' is a terminal). To derive a string 'w' of length 'n' using a grammar in CNF: 1. To generate 'n' terminal symbols, we must use exactly 'n' productions of the form A → a. 2. Each production of the form A → BC increases the number of non-terminals in the sentential form by one (it replaces one non-terminal with two). 3. We start with one non-terminal (the start symbol S). To reach a state where we have 'n' non-terminals (which will then each be replaced by a terminal), we need to increase the count from 1 to 'n'. This requires (n - 1) applications of the rule A → BC. 4. Total steps = (Steps to get n non-terminals) + (Steps to convert n non-terminals to terminals) = (n - 1) + n = 2n - 1. Example: For a string of length n=2, the derivation would be S → BC (1 step), B → a (1 step), C → b (1 step). Total = 3 steps, which matches 2(2) - 1 = 3.

In network theory and electronics, the relationship between voltage (v) and current (i) for a linear resistor is given by Ohm's Law: V = IR. For a non-linear device (such as a diode or a transistor), the relationship is not a straight line. The 'incremental' or 'dynamic' resistance is defined as the ratio of a small change in voltage (dv) to the resulting small change in current (di) at a specific operating point. Mathematically, this is expressed as the derivative of the voltage-current characteristic curve: r = dv/di. In the context of the question, 'dy' represents the change in voltage (often denoted as 'v' or 'y' in some mathematical contexts of network functions) and 'di' represents the change in current. Therefore, dy/di represents the incremental resistance. Why other options are incorrect: - Inductance (L) is defined by the relationship between voltage and the rate of change of current (v = L di/dt). - Capacitance (C) is defined by the relationship between current and the rate of change of voltage (i = C dv/dt).

In electrical network theory, the goal of adjusting the source impedance or adding external impedance to a capacitive load is typically 'Power Factor Correction' or 'Impedance Matching'. A capacitive load causes the current to lead the voltage. To neutralize this effect (to bring the power factor closer to unity or to balance the circuit), an inductive impedance must be introduced. Inductive reactance (XL) and capacitive reactance (XC) act in opposite directions in the complex plane (imaginary axis). Therefore, to offset or compensate for a capacitive nature, the corresponding impedance should be inductive. This process is known as resonance or compensation, where XL = XC, resulting in a purely resistive circuit.

The Commutative Law in Boolean algebra states that the order in which two variables are operated upon (either by OR or AND) does not change the result. For addition (OR), it is expressed as A + B = B + A. For multiplication (AND), it is expressed as A · B = B · A. Analysis of the options: - Option (a) (A + B) + C = A + (B + C) represents the Associative Law, which deals with the grouping of variables. - Option (b) A · (B + C) = (A · B) + (A · C) represents the Distributive Law, which describes how multiplication distributes over addition. - Option (c) A + B = B + A represents the Commutative Law, as it shows that changing the position of the variables does not affect the outcome. - Option (d) A + A = A represents the Idempotent Law, which states that combining a variable with itself using OR or AND results in the original variable.

Thevenin's and Norton's theorems are fundamental tools in network analysis used to simplify a linear circuit into a single source and a single impedance. 1. **Linearity Requirement**: The primary requirement for these theorems to apply is that the network must be 'linear'. A linear network is one where the components (resistors, capacitors, inductors) have constant values and the sources are independent or dependent linear sources. 2. **Independent Sources**: The theorems obviously apply to networks containing only independent voltage or current sources. 3. **Dependent Sources**: The theorems also apply to networks containing dependent (controlled) sources. The only difference is in the method of calculating the equivalent resistance (Thevenin resistance, Rth). While for independent sources we can simply 'kill' the sources (short voltage, open current), for dependent sources, we must either: - Use the Open Circuit Voltage (Voc) and Short Circuit Current (Isc) method: Rth = Voc / Isc. - Apply an external test voltage or current source at the terminals and calculate the resulting response. Therefore, the presence of dependent sources does not invalidate the theorem; it only changes the procedure for finding the equivalent resistance. Options a, b, and c are too restrictive, as they suggest the theorems only work under specific subsets of linear components.

A Half Adder is a combinational circuit that performs the addition of two single-bit binary numbers (A and B). It has two outputs: the Sum and the Carry. 1. The Sum output is generated using an XOR gate, as the binary sum of two bits is 1 only if the inputs are different (0+1=1, 1+0=1) and 0 if they are the same (0+0=0, 1+1=0 in binary addition, where the 1 carries over). 2. The Carry output is generated using an AND gate, as a carry is produced only when both inputs are 1 (1+1 = 10 in binary, where 0 is the sum and 1 is the carry). Therefore, the output of the AND gate in a half adder circuit is the Carry.