MES Jr. Grade • 2018 • Paper-III
Explain different addressing modes of 8085.
MES Jr. Grade • 2018 • Paper-III
Use K-map to minimize the following sop expression: ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
MES Jr. Grade • 2018 • Paper-III
Consider the transistor circuit given below. The transistors have high values of β and VCE = 0.65 Volts. The current I flowing through the 2 KΩ resistance will be:
A)
1 mA
B)
3.33 mA
C)
0 mA
D)
5 mA
With high β, the base currents are negligible, so the transistor pair behaves like a current mirror. The emitter/collector junctions are assumed to be at VCE ≈ 0.65 V, so the voltage across the 2 kΩ resistor is set by the supply and the transistor drop. From the circuit, this gives a resistor current of I = 6.66 V / 2 kΩ = 3.33 mA. Hence option (b) is correct.
Why others are wrong:
- (a) 1 mA: would require only 2 V across the 2 kΩ resistor, which is not consistent with the given transistor drop and circuit bias.
- (c) 0 mA: impossible because the transistor is biased on and the resistor has a nonzero voltage across it.
- (d) 5 mA: would require 10 V across 2 kΩ, which exceeds the available effective voltage in the circuit.
MES Jr. Grade • 2018 • Paper-III
A master slave configuration consists of two identical flip-flops connected in such a way that output of the master is input to slave. Which one of the following is correct?
A)
master is level triggered and salve is edge triggered.
B)
master is edge triggered and salve is level triggered.
C)
master is positive edge triggered and slave is negative edge triggered.
D)
master is negative edge triggered and slave is positive edge triggered.
In a master-slave flip-flop, two level-sensitive latches are connected in cascade and controlled by complementary clock phases. The master responds during one half of the clock cycle, while the slave responds during the opposite half. Effectively, the master captures the input when the clock is low-to-high complementary phase arrangement is considered, and the slave updates the output on the opposite transition. Among the given options, this behavior is best represented by: master is negative edge triggered and slave is positive edge triggered. Options (a) and (b) are incorrect because master-slave operation is not a combination of one level-triggered and one edge-triggered flip-flop. Option (c) reverses the usual complementary triggering order given in this form of the question.
MES Jr. Grade • 2018 • Paper-III
12 MHz clock frequency is applied to a cascaded counter of MOD-3 counter, MOD-4 counter and MOD-5 counter. What are the lowest output frequency and the overall MOD respectively?
A)
200 KHz, 50
B)
1 MHz, 60
C)
3 MHz, 12
D)
4 MHz, 12
For cascaded counters, the overall modulus is the product of individual moduli: 3 × 4 × 5 = 60. Hence overall MOD = 60. The output frequency is the input clock divided by the overall modulus: 12 MHz ÷ 60 = 0.2 MHz = 200 kHz. So the correct frequency should be 200 kHz with MOD 60. However, that exact pair is not present in the options. Among the given choices, option (b) has the correct overall MOD (60), but its frequency is incorrect. Therefore, the question/options appear inconsistent.
MES Jr. Grade • 2018 • Paper-III
In a 8085 microprocessor, the following sequence of instructions is executed: STC, CMC, MOV A, B, RAI, MOV B, A. After the last instruction, the output will:
A)
rotate the contents of the accumulator and store it in B
B)
get the contents of B register into
C)
double contents of B register
D)
manipulate carry in A and B
The instruction sequence is interpreted as: STC sets carry, CMC complements carry, MOV A,B copies B into A, RAI (meant as RAR/RAL-type rotation) rotates the accumulator contents, and MOV B,A copies the modified accumulator back into B. So the net effect is to rotate the contents of the accumulator and store the result in B. Option (b) is incomplete, (c) is not a doubling operation, and (d) is too vague and not the specific outcome.
MES Jr. Grade • 2018 • Paper-III
In an FM Stereo multiplex transmission, the:
A)
sum signal modulates the 19KHz subcarrier
B)
different signal modulates the 19KHz subcarrier
C)
different signal modulates the 38KHz subcarrier
D)
different signal modulates the 67KHz subcarrier
In FM stereo multiplexing, the left and right audio signals are combined into two parts: the sum signal (L+R) and the difference signal (L−R). The sum signal occupies the baseband directly, while the difference signal modulates a 38 kHz suppressed subcarrier using DSB-SC modulation. A 19 kHz pilot tone is also transmitted to help regenerate the 38 kHz subcarrier at the receiver. Therefore, option (c) is correct. Option (a) is wrong because the sum signal does not modulate 19 kHz; option (b) is wrong because 19 kHz is only the pilot tone; option (d) is wrong because 67 kHz is not used for the stereo difference signal.
MES Jr. Grade • 2018 • Paper-III
A 3-phase voltage source inverter is operated in 180° conduction mode. Which one of the following statement is true?
A)
both pole voltage and line voltage will have 3rd harmonics components
B)
pole voltage will have 3rd harmonic component but line voltage will be free from 3rd harmonic
C)
line voltage will have 3rd harmonic component but pole voltage will be free from 3rd harmonic
D)
both pole voltage and line voltage will be free from 3rd harmonic components.
In a 3-phase voltage source inverter operating in 180° conduction mode, each phase (pole) voltage contains odd harmonics, including the 3rd harmonic. However, the 3rd harmonic is a triplen harmonic, and triplen harmonics in all three phase voltages are in phase with each other. When line voltage is obtained by subtracting two phase voltages, these equal in-phase 3rd harmonic components cancel out. Therefore, pole voltage contains 3rd harmonic, but line voltage does not. Hence option (b) is correct. Options (a) and (c) are incorrect because the 3rd harmonic does not appear in line voltage, and (d) is incorrect because pole voltage does contain the 3rd harmonic.
MES Jr. Grade • 2018 • Paper-III
The counter starts off in the 0000 state, and then clock pulses are applied. Sometime later the clock pulses are removed and the counter FFs read 0011. How many clock pulses have occurred?
A)
3
B)
35
C)
51
D)
any of them
A 4-bit counter repeats its states every 16 clock pulses. Starting from 0000, the state 0011 occurs after 3 pulses first. After that, it will again occur after every 16 more pulses: 3, 19, 35, 51, ... Hence 35 and 51 are also possible. Therefore the number of clock pulses could be any value of the form 3 + 16n, so among the given options the correct choice is 'any of them'.
MES Jr. Grade • 2018 • Paper-III
In a single-phase voltage controller with RL load α is the firing angle, φ is the load phase angle and β is the extinction angle. For this voltage controller output power can be controlled if α > φ and:
A)
(β-α) = π
B)
(β-α) < π
C)
β > π
D)
Both (b) & (c)
For a single-phase AC voltage controller with RL load, when the firing angle α is greater than the load phase angle φ, the load current continues beyond π because of inductance. Hence extinction occurs at β > π. In this case conduction is no longer limited to exactly 180°, so the conduction interval becomes (β − α) < π for the power-control region. Therefore both conditions are satisfied: (β − α) < π and β > π. Hence the correct option is (d). Option (a) is for exactly 180° conduction, which is not the relevant controlled RL-load case here.
MES Jr. Grade • 2018 • Paper-III
The data bus in 8080A/8085 microprocessor is a group of:
A)
eight bidirectional lines that are used to transfer 8 bits between the microprocessor and its I/O and memory.
B)
eight lines used to transfer data among the registers
C)
eight unidirectional lines that are used for I/O devices
D)
sixteen bidirectional lines that are used for data transfer between the microprocessor and memory.
The 8080A/8085 are 8-bit microprocessors, so their data bus is 8 bits wide. A data bus must be bidirectional because data is both read from memory/I/O into the microprocessor and written from the microprocessor to memory/I/O. Hence option (a) is correct. Option (b) is incorrect because register transfer inside the CPU is not described as the external data bus. Option (c) is incorrect because the data bus is not unidirectional. Option (d) is incorrect because the 8085 has a 16-bit address bus, not a 16-bit data bus.
MES Jr. Grade • 2018 • Paper-III
During the turn-off process of a thyristor the current flow does not stop at the instant when the current reaches zero but continues to flow to a peak value in the reverse direction. This is due to:
A)
commutation failure
B)
hole storage effect
C)
presence to reverse voltage across the thyristor
D)
protection inductance in series with the thyristor
When a thyristor turns off, the forward current falls to zero, but stored charge carriers inside the device do not disappear instantly. Due to charge storage, especially holes accumulated in the layers, a reverse recovery current flows for a short time and may reach a peak in the reverse direction before decaying to zero. This is called the hole storage effect.
Why others are incorrect: (a) Commutation failure means the thyristor fails to turn off properly, not the normal cause of reverse recovery current. (c) Reverse voltage helps drive the recovery current but is not the fundamental physical cause. (d) Series inductance opposes change in current; it is not the main reason for the reverse current peak during turn-off.
MES Jr. Grade • 2018 • Paper-III
Which of the following statements is true?
A)
ROM is a Read/Write memory
B)
PC points to the last instruction that was executed
C)
Stack works on the principle of LIFO
D)
All instructions affect the flags
The correct statement is (c) because a stack follows the principle of LIFO (Last In, First Out): the last item inserted is the first one removed.
Why the other options are incorrect:
(a) ROM is not a Read/Write memory in normal operation; it is Read Only Memory.
(b) The Program Counter (PC) points to the next instruction to be executed, not the last instruction executed.
(d) All instructions do not affect the flags; only certain arithmetic, logical, or comparison instructions modify flag bits.
MES Jr. Grade • 2018 • Paper-III
Diffusion of impurities in a semiconductor is carried out in a furnace through which a steady stream of impurity atoms is passed during the entire diffusion process. What would be the type of profile of the impurity atoms inside the semiconductor?
A)
Linear
B)
Gaussian
C)
Complementary error function
D)
Exponential
When diffusion is carried out with a steady supply of impurity atoms throughout the process, the surface concentration remains constant. This is called constant-source diffusion. For constant-source diffusion in a semiconductor, the impurity concentration profile inside the semiconductor follows the complementary error function (erfc): C(x,t) = Cs erfc[x/(2√Dt)].
Why others are incorrect:
(a) Linear: diffusion profiles are not linear in this case.
(b) Gaussian: Gaussian profile occurs in limited-source (instantaneous or finite-dose) diffusion, not constant-source diffusion.
(d) Exponential: not the standard solution for impurity diffusion in this semiconductor process.
MES Jr. Grade • 2018 • Paper-III
Describe a gate triggering circuit for a single phase full converter. Discuss how the adjustment of control voltage varies the firing delay angle.
MES Jr. Grade • 2018 • Paper-III
With neat circuit diagram explain the working principle of single phase semi converter draw its waveforms.
MES Jr. Grade • 2018 • Paper-III
What is PWM? What are its advantages? Explain sine pulse width modulation technique.
MES Jr. Grade • 2018 • Paper-III
Explain principle of operation of time ratio control & current limit control strategies for Chopper circuit.
MES Jr. Grade • 2018 • Paper-III
Explain mono stable Multivibrator using IC555.
MES Jr. Grade • 2018 • Paper-III
Explain operation of CB configuration with neat circuit diagram and output characteristics of CB mode BJT.
MES Jr. Grade • 2018 • Paper-III
When RET instruction is executed by any subroutine then:
A)
the top of the stack will be popped out and assigned to the PC
B)
without any operation, the calling program would resume from instruction immediately following the call instruction.
C)
the PC will be incremented after the execution of the instruction
D)
without any operation, the calling program would resume from instruction immediately following the call instruction, and also the PC will be incremented after the execution of the instruction.
In a microprocessor, when a subroutine is called using CALL, the return address (address of the next instruction in the calling program) is pushed onto the stack. When RET is executed, that saved return address is popped from the top of the stack and loaded into the Program Counter (PC). This causes execution to resume at the instruction immediately following the CALL. Hence option (a) is correct. Options (b), (c), and (d) are incorrect because RET does not resume 'without any operation'; it specifically performs a stack pop into the PC, and the return is not achieved merely by incrementing the PC.
MES Jr. Grade • 2018 • Paper-III
Communication system is to be designed to provide an output SNR of 30dB. The ratio is measured from bandwidth point of view which of the following modulation is preferred?
A)
FM
B)
PCM
C)
Both are having same band width
D)
None
For a required output SNR of 30 dB, bandwidth efficiency is the deciding factor here. In FM, to achieve higher output SNR, the required transmission bandwidth increases significantly because FM improvement depends on deviation ratio and Carson’s rule gives a comparatively large bandwidth. In PCM, the output SNR depends on the number of quantization bits, and for 30 dB only a moderate number of bits is needed, making it more bandwidth-efficient from the bandwidth point of view in such comparisons. Hence PCM is preferred. Therefore, option (b) is correct. Options (a), (c), and (d) are incorrect because FM generally requires larger bandwidth for the same output SNR, they do not have the same bandwidth, and one valid choice does exist.
MES Jr. Grade • 2018 • Paper-III
In a bistable multivibrator, commuting capacitors are used to:
A)
increase the base storage charge
B)
provide a.c. coupling
C)
increase the speed of response
D)
alter the frequency of the output
In a bistable multivibrator, commutating (often written as commuting in some questions) capacitors are connected to speed up the switching transition from one stable state to the other. They provide a short pulse during switching, which helps remove stored charge in the transistor and makes the circuit respond faster. Hence, they are used to increase the speed of response.
Why others are incorrect: (a) They do not increase base storage charge; in fact, faster switching is aided by reducing storage effects. (b) Their main purpose here is not general a.c. coupling. (d) A bistable multivibrator has two stable states and no free-running frequency, so frequency alteration is not the purpose.
MES Jr. Grade • 2018 • Paper-III
Shifting a register to the left by one bit position is equivalent to (in Binary code):
A)
division by 2
B)
multiplication by 2
C)
addition of 2
D)
subtraction of 2
In binary, shifting all bits of a register one position to the left moves each bit to the next higher place value. This doubles the value of the number, provided overflow is ignored. For example, 0101 (5) becomes 1010 (10), which is 5 × 2. Therefore, left shift by one bit is equivalent to multiplication by 2. Division by 2 corresponds to a right shift, and addition/subtraction by 2 do not generally match a left shift.
MES Jr. Grade • 2018 • Paper-III
Discuss the principle of working of a three phase bridge inverter with an appropriate circuit diagram. Draw phase and line voltage waveforms on the assumption that each thyristor conducts for 120° and the resistive load is star-connected. The sequence of firing of various SCRs should also be indicated in the diagram.
