Past Questions — 2024

Step-by-step reasoning: 1. **Definition of an R-S Latch**: An R-S (Reset-Set) latch is a basic digital circuit used to store the state of a binary digit. It is constructed using cross-coupled NOR or NAND gates. 2. **Memory Capability**: Because of the feedback loop (cross-coupling), the circuit can maintain its output state (either 0 or 1) even after the input signals are removed. This ability to 'remember' a state makes it a memory element. 3. **Storage Capacity**: A single R-S latch can store exactly one binary digit (0 or 1), which is defined as one bit of information. Evaluating the options: - **Option (a) combinational circuit**: Incorrect. Combinational circuits have outputs that depend solely on current inputs. Latches have feedback, making them sequential circuits. - **Option (b) synchronous sequential circuit**: Incorrect. An R-S latch is an *asynchronous* sequential circuit because it does not require a clock signal to change its state; it responds to input changes immediately. - **Option (c) one clock delay element**: Incorrect. A latch is not used as a delay element, and basic R-S latches are not clock-driven. - **Option (d) one bit memory element**: Correct. As established, it stores one bit of data based on the Set and Reset inputs.

The operating point (or Q-point) of an amplifier is the specific DC voltage and current level at which the active device (transistor) is biased. This point is determined by the DC biasing circuit, which is directly powered by the DC power supply (Vcc). 1. Why 'd' is correct: If the power supply voltage fluctuates, the DC voltages across the biasing resistors change, which directly alters the base-emitter voltage (Vbe) and collector-emitter voltage (Vce), causing the Q-point to shift. This can lead to signal clipping or distortion. 2. Why 'a' is incorrect: Input frequency variation affects the gain and bandwidth (AC response) of the amplifier due to coupling and bypass capacitors, but it does not change the DC bias levels. 3. Why 'b' is incorrect: Noise at the input is an unwanted AC signal. While it may be amplified, it does not shift the static DC operating point of the transistor. 4. Why 'c' is incorrect: Parasitic capacitances affect the high-frequency response (cutoff frequency) of the amplifier, but they do not influence the DC biasing conditions.

In a Common Gate (CG) amplifier configuration, the input signal is applied to the source terminal and the output is taken from the drain terminal, while the gate is common (grounded). 1. **Input Resistance (Rin):** The input signal enters through the source. The input resistance is approximately equal to 1/gm (where gm is the transconductance of the FET). Since gm is typically large, 1/gm is small, resulting in a low input resistance. This makes the CG amplifier useful for impedance matching with low-impedance sources. 2. **Output Resistance (Rout):** The output is taken from the drain. The output resistance is determined by the drain-to-source resistance (rd) in parallel with the drain resistor (Rd). Since rd is typically very high for FETs, the overall output resistance remains high. Comparing this to other configurations: - Common Source (CS): High Rin, High Rout. - Common Drain (CD/Source Follower): High Rin, Low Rout. - Common Gate (CG): Low Rin, High Rout.

To find the angle of incidence for total internal reflection (TIR), we use Snell's Law. Total internal reflection occurs when a wave travels from a denser medium (higher refractive index) to a rarer medium (lower refractive index) at an angle greater than the critical angle (θc). 1. **Identify the given values:** - Relative permittivity of medium 1 (εr1) = 2 - Relative permittivity of medium 2 (εr2) = 1 2. **Relationship between Refractive Index (n) and Permittivity (εr):** The refractive index is given by n = √(εr * μr). Assuming both media are non-magnetic (μr = 1): - n1 = √(εr1) = √2 - n2 = √(εr2) = √1 = 1 3. **Formula for Critical Angle (θc):** According to Snell's Law, at the critical angle, the angle of refraction is 90°. sin(θc) = n2 / n1 sin(θc) = 1 / √2 4. **Calculate θc:** sin(θc) = 1/√2 implies θc = arcsin(1/√2) = 45°. Therefore, for total reflection to occur, the angle of incidence must be equal to or greater than 45°. Among the given options, 45° is the threshold angle for total reflection.

The scenario describes a standard 'two-way switch' system used in staircases. Let the two switches be represented by inputs A and B, and the state of the bulb be the output Y. 1. Analysis of the requirement: 'The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch.' This means that flipping either switch must change the current state of the bulb (from ON to OFF or OFF to ON). 2. Truth Table Construction: - If both switches are in the same position (both DOWN or both UP), let's assume the bulb is OFF (Y=0). - If one switch is flipped (one UP, one DOWN), the bulb turns ON (Y=1). - If the other switch is then flipped to match the first one, the bulb turns OFF (Y=0). Truth Table: - A=0, B=0 -> Y=0 - A=0, B=1 -> Y=1 - A=1, B=0 -> Y=1 - A=1, B=1 -> Y=0 3. Logic Gate Identification: - The truth table above (0, 1, 1, 0) corresponds exactly to the Exclusive-OR (XOR) logic gate. - An AND gate would only be ON if both are 1. - An OR gate would be ON if either or both are 1. - A NAND gate would be OFF only if both are 1. Therefore, the logic of the staircase switching system is that of an XOR gate.

Option D is correct: 1.25 kHz.

Option D is correct: +90°.

Step-by-step derivation of the sensitivity of a closed-loop system: 1. **Define the Overall Transfer Function (M):** For a standard closed-loop control system with forward path gain G(s) and feedback path gain H(s), the overall transfer function M is given by: M = G(s) / [1 + G(s)H(s)] 2. **Define Sensitivity (S):** Sensitivity of a system transfer function M with respect to a parameter G is defined as the ratio of the fractional change in M to the fractional change in G: S^M_G = (dM / M) / (dG / G) = (dM / dG) * (G / M) 3. **Calculate the Derivative (dM/dG):** Using the quotient rule [d/dx (u/v) = (v u' - u v') / v^2]: Let u = G and v = 1 + GH dM/dG = [ (1 + GH)(1) - (G)(H) ] / (1 + GH)^2 dM/dG = [ 1 + GH - GH ] / (1 + GH)^2 = 1 / (1 + GH)^2 4. **Substitute back into the Sensitivity formula:** S^M_G = [ 1 / (1 + GH)^2 ] * [ G / (G / (1 + GH)) ] S^M_G = [ 1 / (1 + GH)^2 ] * [ 1 + GH ] S^M_G = 1 / (1 + G(s)H(s)) Conclusion: The sensitivity of the closed-loop gain to variations in the forward path gain G is 1 / (1 + G(s)H(s)). This demonstrates that increasing the open-loop gain (GH) reduces the sensitivity, making the system more robust to parameter variations. Options b, c, and d do not follow the mathematical derivation of sensitivity.

1. **Understanding the Device**: The question specifies a p-channel JFET. In a p-channel JFET, the carriers are holes, and the polarities of the voltages are opposite to those of an n-channel JFET. 2. **Given Parameters**: - Pinch-off voltage ($V_p$) = $+6 ext{V}$ - Gate-to-Source voltage ($V_{GS}$) = $+2 ext{V}$ 3. **Saturation Condition**: A FET enters the saturation region (also known as the pinch-off region) when the drain-to-source voltage ($V_{DS}$) reaches the saturation voltage ($V_{DS(sat)}$). The formula for the saturation voltage is: $V_{DS(sat)} = V_{GS} - V_p$ 4. **Calculation**: $V_{DS(sat)} = (+2 ext{V}) - (+6 ext{V})$ $V_{DS(sat)} = -4 ext{V}$ 5. **Verification of Polarities**: For a p-channel FET, $V_{GS}$ is positive (to keep the channel open) and $V_{DS}$ must be negative to allow current to flow from source to drain. A value of $-4 ext{V}$ is physically consistent with the operation of a p-channel device. 6. **Analysis of Options**: - (a) $-6 ext{V}$: Incorrect. This would be the saturation voltage if $V_{GS} = 0 ext{V}$. - (b) $-4 ext{V}$: Correct. Matches the calculation $V_{GS} - V_p$. - (c) $+8 ext{V}$: Incorrect. This uses the wrong sign convention. - (d) $+4 ext{V}$: Incorrect. $V_{DS}$ must be negative for a p-channel FET to operate in the active/saturation region.

A Master-Slave flip-flop is designed to eliminate the 'race-around condition' found in level-triggered JK flip-flops. It consists of two cascaded flip-flops: the Master and the Slave. 1. **The Master Flip-Flop**: This stage is level-triggered. When the clock signal is high (or low, depending on the design), the master flip-flop is enabled and accepts inputs, updating its state based on the input signals. However, the slave is disabled during this period. 2. **The Slave Flip-Flop**: The slave is triggered by the opposite level or the transition (edge) of the clock. In a standard Master-Slave configuration, the clock signal is inverted before it reaches the slave. Therefore, while the master is active during the level, the slave only updates its output to match the master's state when the clock transitions (the edge). Effectively, the Master-Slave configuration acts as a pulse-triggered or edge-triggered device. The master samples the input during the clock level, and the slave transfers that sampled value to the output on the clock edge. Comparing the options: - Option (a) correctly identifies that the master operates on the level and the slave operates on the transition/edge. - Options (b), (c), and (d) are incorrect because the master cannot be edge-triggered if the goal is to sample the input over a duration and then transfer it on a specific transition.

A T (Toggle) flip-flop is a modification of a JK flip-flop where the J and K inputs are tied together to a single input T. The characteristic equation describes the next state (Q*) based on the current state (Q) and the input (T). 1. **Truth Table Analysis**: - If T = 0: The flip-flop holds its current state. So, Q* = Q. - If T = 1: The flip-flop toggles its current state. So, Q* = Q'. 2. **Deriving the Equation**: Using a Karnaugh Map or Boolean algebra: Q* = (T' AND Q) OR (T AND Q') Q* = T'Q + TQ' 3. **Evaluating Options**: - Option (a) Q* = TQ' + T'Q: This matches the derived characteristic equation (the XOR operation). - Option (b) Q* = TQ + T'Q: This simplifies to Q* = Q(T + T') = Q, which is only true when T=0. - Option (c) Q* = TQ: This is incorrect as it doesn't account for the toggle or hold conditions correctly. - Option (d) Q* = T'Q: This is incorrect as it ignores the case where T=1 and Q=0.

An ideal Operational Amplifier (Op-amp) is characterized by its ability to amplify the difference between its two input voltages. 1. **Input Characteristics**: An ideal Op-amp has infinite input impedance, meaning it draws zero current from the source. Therefore, the control signal is the differential input voltage (Vdiff = V+ - V-). 2. **Output Characteristics**: An ideal Op-amp has zero output impedance, meaning it can supply any amount of current to a load to maintain a specific output voltage. This makes the output a voltage source. 3. **Transfer Function**: The output voltage is given by Vout = A * (V+ - V-), where 'A' is the open-loop gain. Since the output voltage (Vout) is determined by the input voltage (Vdiff), it is mathematically defined as a Voltage Controlled Voltage Source (VCVS). Why other options are incorrect: - (a) Voltage Controlled Current Source (VCCS): This would describe a device like a MOSFET (where gate voltage controls drain current), but an Op-amp's primary purpose is to provide a voltage output. - (b) Current Controlled Current Source (CCCS): This describes certain transistor configurations, not an Op-amp. - (d) Current Controlled Voltage Source (CCVS): This describes a device where the input is a current (like a transimpedance amplifier), but the fundamental ideal model of an Op-amp is based on voltage difference control.

Step 1: Simplify the given expression Y = ABC + A'BC + AB'C + ABC'. We can group the terms to simplify using Boolean algebra: - Group 1: ABC + A'BC = BC(A + A') = BC(1) = BC - Group 2: ABC + AB'C = AC(B + B') = AC(1) = AC - Group 3: ABC + ABC' = AB(C + C') = AB(1) = AB Wait, the expression is Y = ABC + A'BC + AB'C + ABC'. Let's group them more efficiently: Y = (ABC + A'BC) + (AB'C + ABC') Actually, let's use the common term ABC: Y = ABC + A'BC + AB'C + ABC' Y = BC(A + A') + AC(B + B') - ABC (since ABC was used twice) Alternatively: Y = BC(A + A') + AB(C + C') + AB'C Let's use a K-map or simple grouping: Term 1 & 2: BC(A + A') = BC Term 1 & 3: AC(B + B') = AC Term 1 & 4: AB(C + C') = AB So, Y = AB + BC + AC. Step 2: Find the complement of Y (Y'). Y' = (AB + BC + AC)' Using De Morgan's Law: Y' = (AB)' . (BC)' . (AC)' Y' = (A' + B') . (B' + C') . (A' + C') Step 3: Simplify the complement expression. Y' = (A' + B')(B' + C')(A' + C') Multiply the first two brackets: (A'B' + A'C' + B'B' + B'C')(A' + C') Since B'B' = B': (A'B' + A'C' + B' + B'C')(A' + C') Since B' + B'C' = B'(1 + C') = B': (A'B' + A'C' + B')(A' + C') Since B' + A'B' = B'(1 + A') = B': (B' + A'C')(A' + C') Now multiply by (A' + C'): B'A' + B'C' + A'C'A' + A'C'C' = A'B' + B'C' + A'C' + A'C' = A'B' + B'C' + A'C' Step 4: Factorize the result. This is the dual of the original expression. Let's check the options provided. The options provided in the prompt are identical (a, b, c, d are all (A+B)(A+C)), which suggests a typo in the source exam paper. However, mathematically, the complement of (AB + BC + AC) is (A' + B')(B' + C')(A' + C'). If we look at the options provided in the prompt, they are all (A+B)(A+C). If the original expression was Y = A'B' + B'C' + A'C', then the complement would be (A+B)(B+C)(A+C). Given the options provided are identical and likely corrupted, but the standard simplification of the complement of the 'majority function' (AB+BC+AC) leads to the product of sums of the complements. However, if the question intended Y = A'B' + B'C' + A'C', the answer would be (A+B)(B+C)(A+C). Given the options provided are all the same, we select 'a' as the representative correct choice for the simplified form of the complement of the dual, though the options provided in the prompt text are likely truncated or repeated. Based on the logic of the expression Y = AB+BC+AC, the complement is Y' = A'B' + B'C' + A'C'.

To determine the stability of the system, we use the Routh-Hurwitz stability criterion. The characteristic polynomial is q(s) = 2s^5 + s^4 + 4s^3 + 2s^2 + 2s + 1. Step 1: Construct the Routh Array - s^5: 2, 4, 2 - s^4: 1, 2, 1 - s^3: [(1*4 - 2*2)/1, (1*2 - 2*1)/1] = [0, 0] Step 2: Handle the Row of Zeros Since the s^3 row consists entirely of zeros, we have a special case indicating the presence of roots symmetric about the origin. We form an auxiliary equation A(s) using the coefficients of the row immediately above (s^4): A(s) = 1s^4 + 2s^2 + 1 = 0 Step 3: Differentiate the Auxiliary Equation To continue the array, we take the derivative of A(s) with respect to s: dA(s)/ds = 4s^3 + 4s Step 4: Complete the Routh Array using the derivative coefficients (4, 4) - s^5: 2, 4, 2 - s^4: 1, 2, 1 - s^3: 4, 4 (from derivative) - s^2: [(4*2 - 1*4)/4, (4*1 - 1*0)/4] = [1.5, 1] (Wait, let's re-calculate: [(4*2 - 4*1)/4] = 1; [(4*1 - 4*0)/4] = 1. Let's be precise: s^2 coeff = (4*2 - 4*1)/4 = 1; (4*1 - 4*0)/4 = 1) - s^1: [(1*4 - 4*1)/1] = 0 Step 5: Analyze the results We encounter another row of zeros at s^1. Let's re-examine the auxiliary equation A(s) = s^4 + 2s^2 + 1 = (s^2 + 1)^2. This means the roots are s = ±j, ±j (repeated roots on the imaginary axis). According to stability theory: 1. If there are any roots in the Right Half Plane (RHP), the system is unstable. 2. If there are non-repeated roots on the imaginary axis and no roots in the RHP, the system is marginally stable. 3. If there are repeated roots on the imaginary axis, the system is unstable because the time response will contain terms like t*sin(wt), which grow linearly over time. Since the roots s = ±j are repeated, the system is unstable.

1. **Identify Given Parameters**: - Characteristic Impedance ($Z_0$) = $50\ \Omega$ - Termination Impedance ($Z_L$) = $-50\ \Omega$ 2. **Calculate the Reflection Coefficient ($\Gamma$)**: The reflection coefficient at the load is given by the formula: $$\Gamma = \frac{Z_L - Z_0}{Z_L + Z_0}$$ Substituting the given values: $$\Gamma = \frac{-50 - 50}{-50 + 50} = \frac{-100}{0}$$ Mathematically, a division by zero results in an undefined value, but in the context of limits for reflection coefficients, this indicates a total reflection where the magnitude $|\Gamma| = 1$. 3. **Calculate the Voltage Standing Wave Ratio (VSWR)**: The formula for VSWR is: $$\text{VSWR} = \frac{1 + |\Gamma|}{1 - |\Gamma|}$$ Substituting $|\Gamma| = 1$: $$\text{VSWR} = \frac{1 + 1}{1 - 1} = \frac{2}{0} = \infty$$ 4. **Conclusion**: A termination of $-50\ \Omega$ (which represents a purely reactive load with a specific phase or a theoretical negative resistance) creates a condition where the denominator of the reflection coefficient becomes zero, leading to a reflection coefficient magnitude of 1. When $|\Gamma| = 1$, the VSWR is infinite, indicating a total reflection of the incident wave.

The goal of speeding up computer processing involves reducing the time the CPU spends waiting for data from the main memory (RAM). 1. **Cache Memory (Correct):** This is a small, high-speed volatile memory located very close to or inside the CPU. It stores frequently accessed data and instructions. Because it operates at speeds much closer to the CPU's clock speed than RAM does, it significantly reduces the average time to access data, thereby speeding up overall processing. 2. **BIOS (Incorrect):** The Basic Input/Output System is firmware used to perform hardware initialization during the booting process. It does not speed up general processing. 3. **RAM (Incorrect):** Random Access Memory is the primary working memory. While necessary for the computer to function, it is significantly slower than cache memory. The CPU often has to wait for RAM to deliver data (the 'memory wall'), which is why cache is implemented to bridge this gap. 4. **ROM (Incorrect):** Read-Only Memory is non-volatile memory used to store permanent data (like the BIOS). It is slow and cannot be used for the dynamic data processing required to speed up the CPU.

To determine the number of flip-flops required for a binary counter, we use the formula: 2^n ≥ N, where 'n' is the number of flip-flops and 'N' is the total number of states the counter needs to represent. 1. The counter needs to count from 0 to 1023. 2. The total number of states (N) is 1023 - 0 + 1 = 1024 states. 3. We need to find the smallest integer 'n' such that 2^n ≥ 1024. 4. Calculating powers of 2: 2^7 = 128 2^8 = 256 2^9 = 512 2^10 = 1024 5. Since 2^10 equals exactly 1024, 10 flip-flops are required to represent all values from 0 to 1023. Comparing with options: - Option (a) 7: 2^7 = 128 (Insufficient) - Option (b) 10: 2^10 = 1024 (Correct) - Option (c) 16: 2^16 = 65536 (Excessive) - Option (d) 25: 2^25 = 33,554,432 (Excessive)

Step-by-step reasoning: 1. **Understand the Resolution**: In an Analog-to-Digital Converter (ADC), the resolution is the smallest change in the analog input voltage that can be detected. For a 10-bit ADC, there are $2^{10} = 1024$ discrete levels. 2. **Calculate the Step Size (LSB)**: The resolution (or the value of the Least Significant Bit, LSB) is calculated by dividing the full-scale voltage range by the number of levels: $$\text{Resolution} = \frac{V_{FS}}{2^n} = \frac{5\text{ V}}{1024} \approx 4.88\text{ mV}$$ 3. **Analyze the Ripple Voltage**: If the DC supply voltage (which often serves as the reference voltage $V_{ref}$ for the ADC) has a ripple, this ripple is superimposed on the conversion process. To prevent the ripple from causing a change in the digital output (i.e., to avoid introducing a digital error of $\pm 1$ LSB), the peak-to-peak ripple voltage must be less than or equal to the resolution of the converter. 4. **Conclusion**: The maximum allowable ripple voltage is approximately $4.88\text{ mV}$. Among the given options, $5\text{ mV}$ is the closest value. Comparing options: - a. 100mV: Much larger than 1 LSB; would cause significant noise in the digital output. - b. 50mV: Much larger than 1 LSB. - c. 25mV: Larger than 1 LSB. - d. 5mV: Closest to the calculated resolution of 4.88mV.

Step-by-step solution: 1. **Identify the General Form**: The general transfer function of a lead-lag compensator is given by: G(s) = (s + z) / (s + p) or in time-constant form: G(s) = (Ts + 1) / (αTs + 1). 2. **Analyze the Given Transfer Function**: C(s) = (2s + 1) / (0.2s + 1). Comparing this to the standard form (Ts + 1) / (αTs + 1): - T = 2 - αT = 0.2 3. **Determine the Nature of the Controller**: - In a **Lead Controller**, the zero is closer to the origin than the pole (T < αT, or α < 1). This results in a phase lead. - In a **Lag Controller**, the pole is closer to the origin than the zero (T > αT, or α > 1). This results in a phase lag. - Here, T = 2 and αT = 0.2. Since the time constant of the numerator (2) is greater than the time constant of the denominator (0.2), the pole is closer to the origin. Therefore, it is a **Lag Controller**. 4. **Calculate the Parameter α**: Using the relation αT = 0.2 and T = 2: α * 2 = 0.2 α = 0.2 / 2 = 0.1 **Wait, let's re-evaluate the standard notation**: In many textbooks, the lag compensator is written as G(s) = (s + 1/T) / (s + 1/αT) where α > 1. Alternatively, if written as (Ts + 1) / (αTs + 1), then for a Lag compensator, α > 1 is not the standard; usually, it's written as (s + 1/T) / (s + 1/αT) where α is the attenuation factor. Let's look at the ratio of the time constants: Ratio = (Numerator Time Constant) / (Denominator Time Constant) = 2 / 0.2 = 10. In the context of the provided options, α represents this ratio. Since the numerator time constant (2) is larger than the denominator time constant (0.2), the zero is at s = -0.5 and the pole is at s = -5. Actually, let's re-calculate: Zero: 2s + 1 = 0 => s = -0.5 Pole: 0.2s + 1 = 0 => s = -5 Since the zero is closer to the origin than the pole (|z| < |p|), this is actually a **Lead Controller**. **Correction**: Lead: Zero is closer to origin than pole. (z = 0.5, p = 5). Lag: Pole is closer to origin than zero. Let's re-examine the options. If it is a Lead controller, α = z/p = 0.5/5 = 0.1. Looking at the options: Option (c) says Lead controller, α = 0.1. Option (a) says Lag controller, α = 10. In control systems, the parameter α is often defined as the ratio of the pole to the zero (p/z) for lag or zero to pole (z/p) for lead. For this function: z = 0.5, p = 5. Since z < p, it is a Lead Compensator. α = z/p = 0.5/5 = 0.1. However, in many competitive exam keys for this specific question, the terminology is flipped or α is defined as p/z. If α = p/z = 5/0.5 = 10, and it's labeled as Lag, that would be incorrect. Let's re-verify: C(s) = (2s + 1)/(0.2s + 1). At s=0, C(0) = 1. At s=∞, C(∞) = 2/0.2 = 10. Since the high-frequency gain (10) is greater than the low-frequency gain (1), it is a **Lead Controller**. The lead ratio α = (High freq gain) / (Low freq gain) = 10 / 1 = 10. Wait, usually α for lead is defined as z/p (which is 0.1). Let's check the options again. If it is a Lead controller, α = 0.1 (Option c). If the question defines α as the gain increase (10), it's still a Lead controller. Re-calculating: Zero = -1/2 = -0.5 Pole = -1/0.2 = -5 Zero is closer to origin -> Lead. α = z/p = 0.5/5 = 0.1. Therefore, Option (c) is the technically correct answer based on standard control theory.

Voltage regulation is a measure of the ability of a power supply to maintain a constant output voltage regardless of the load. The formula for voltage regulation is given by: Voltage Regulation (%) = [(V_no_load - V_full_load) / V_full_load] × 100 Given values: - Full-load voltage (V_full_load) = 24 V - Voltage Regulation = 5% = 0.05 Plugging these into the formula: 0.05 = (V_no_load - 24) / 24 Solving for V_no_load: 0.05 * 24 = V_no_load - 24 1.2 = V_no_load - 24 V_no_load = 24 + 1.2 V_no_load = 25.2 V Rounding to the nearest integer as requested in the question, we get 25 V. Analysis of options: - a. 6V: Incorrect. This is significantly lower than the full-load voltage. - b. 12V: Incorrect. This is lower than the full-load voltage. - c. 23V: Incorrect. No-load voltage must be higher than full-load voltage in a standard power supply due to internal resistance/voltage drops. - d. 25V: Correct. This matches our calculated value of 25.2 V rounded to the nearest integer.

Option B is correct: 5.39.

1. The formula for the capacitance (C) of a parallel plate capacitor is given by C = (ε₀A)/d, where ε₀ is the permittivity of free space, A is the area of the plates, and d is the distance between the plates. 2. Initial State: The plates are square with side length L1 = 10 cm. Therefore, the initial area A1 = L1 × L1 = 10 cm × 10 cm = 100 cm². 3. Final State: The plates are reduced to square plates with side length L2 = 2.5 cm. Therefore, the new area A2 = L2 × L2 = 2.5 cm × 2.5 cm = 6.25 cm². 4. Relationship: Since the distance (d) and the dielectric (air) remain constant, the capacitance is directly proportional to the area (C ∝ A). 5. Calculation: The ratio of the new capacitance (C') to the original capacitance (C) is C'/C = A2/A1. 6. Substituting the values: C'/C = 6.25 / 100 = 1/16. 7. Therefore, C' = C/16. Comparing this to the options: - Option a (C/4) is incorrect as it assumes a linear reduction in area rather than square. - Option b (C/8) is incorrect. - Option c (C/16) matches our calculation. - Option d (C/32) is incorrect.

A Phase-Locked Loop (PLL) is a feedback system that tracks the phase and frequency of an input signal. It consists of three main components: a Phase Detector (PD), a Low Pass Filter (LPF), and a Voltage Controlled Oscillator (VCO). 1. **Mechanism**: The Phase Detector compares the phase of the input signal with the phase of the VCO output. It produces an error signal proportional to the phase difference. 2. **Lock Condition**: 'Lock' occurs when the PLL is able to maintain a constant phase difference between the input signal and the VCO output. For the phase difference to remain constant over time, the rate of change of phase (which is frequency) must be identical for both signals. 3. **Frequency Synchronization**: Therefore, in a locked state, the VCO frequency exactly tracks and matches the input frequency (f_in = f_vco). Analysis of other options: - Option b: A phase error of 180° may occur in some configurations, but it is not the defining condition for 'lock'; lock is defined by frequency synchronization. - Option c: If the VCO frequency is double the input frequency, the system is not locked (unless it is a specific frequency multiplier circuit, but the general definition of a PLL lock is frequency matching). - Option d: A phase error of 90° is a specific state but not the general condition for lock.

A Flash Analog-to-Digital Converter (ADC) is the fastest type of ADC because it uses a series of comparators to convert an analog signal to digital in a single clock cycle. 1. **Formula**: For an n-bit Flash ADC, the number of comparators required is given by the formula: Number of Comparators = 2^n - 1 2. **Calculation**: In this problem, the resolution is 4 bits (n = 4). Number of Comparators = 2^4 - 1 Number of Comparators = 16 - 1 Number of Comparators = 15 3. **Analysis of Options**: - Option (a) 67 and (b) 77 are mathematically unrelated to the 2^n - 1 formula for 4 bits. - Option (d) 11 is incorrect. - Option (c) 15 matches the calculated value exactly.

In a Bode magnitude plot, the slope of the high-frequency asymptote is determined by the difference between the number of poles and the number of zeros in the system's transfer function. 1. **Identify the given parameters:** - Number of poles (n) = 14 - Number of zeros (m) = 2 2. **Formula for the final slope:** The slope of the magnitude plot at high frequencies is given by: Slope = (m - n) × 20 dB/decade 3. **Calculation:** Slope = (2 - 14) × 20 dB/decade Slope = (-12) × 20 dB/decade Slope = -240 dB/decade Therefore, the slope of the highest frequency asymptote is -240 dB/decade. Option (b) is correct. Options (a), (c), and (d) are incorrect as they result from incorrect calculations of the pole-zero difference.