← MES Jr. Grade
Past Questions
Which one of the following in NOT necessarily a property of a Group?
A)
Commutativity
B)
Associativity
C)
Existence of inverse for every element
D)
Existence of identity
Based on established principles in Quantitative Aptitude, the correct and most appropriate choice is 'Commutativity' (Option A).
If two finite states machine M and N are isomorphic, then
A)
M can be transformed to N, merely re-labelling its states
B)
M can be transformed to N, merely re-labelling its edges
C)
Both (a) & (b)
D)
None of these
Based on established principles in the relevant subject area, the correct and most appropriate choice is 'M can be transformed to N, merely re-labelling its edges' (Option B).
Power set of empty or Null set has exactly ________ subset.
A)
One
B)
Three
C)
Two
D)
Zero
Based on established principles in Quantitative Aptitude, the correct and most appropriate choice is 'Zero' (Option D).
How many rows are needed in the primitive flow table for the gated latch?
A)
1 row
B)
3 rows
C)
5 rows
D)
7 rows
Based on established principles in Electrical / Electronics Engineering, the correct and most appropriate choice is '3 rows' (Option B).
The circuit shown in figure is a 3 input gate of type:
A)
NOR
B)
NAND
C)
OR
D)
AND
Based on established principles in the relevant subject area, the correct and most appropriate choice is 'OR' (Option C).
In a multi stage R-C coupled amplifier the coupling capacitor
A)
limits the low frequency response
B)
limits the high frequency response
C)
does not affect the frequency response
D)
block the d.c. component without affecting the frequency response
In a multi-stage R-C coupled amplifier, the coupling capacitor passes the AC signal from one stage to the next while blocking DC. At low frequencies, its reactance becomes large, so less signal is coupled and the amplifier gain falls. Therefore, it limits the low-frequency response.
Why others are wrong:
- d: It is true that the capacitor blocks DC, but it does affect frequency response at low frequencies.
- b: High-frequency response is mainly limited by internal and stray capacitances, not the coupling capacitor.
- c: Incorrect because the coupling capacitor does affect the frequency response, especially at low frequencies.
The race around condition exists in J-K flip flop if
A)
J=0; K=1
B)
J=1; K=0
C)
J=0; K=0
D)
J=1; K=1
The race-around condition in a J-K flip-flop occurs when J=1 and K=1, especially in a level-triggered J-K flip-flop. In this case, while the clock remains active, the output keeps toggling repeatedly instead of settling to a single stable state. This is the classic race-around problem.
Why the other options are incorrect:
- J=1, K=0: This is the set condition; the output is driven to 1 and does not race.
- J=0, K=1: This is the reset condition; the output is driven to 0 and does not race.
- J=0, K=0: This is the hold condition; the output remains unchanged and does not race.
In an 8085 microprocessor system with memory mapped I/O
A)
I/O devices have 16 bit addresses
B)
I/O devices are accessed using IN and OUT instruction
C)
there can be a maximum of 256 input devices and 256 output devices
D)
arithmetic and logic operations can be directly performed with the I/O data
In an 8085 system with memory-mapped I/O, I/O devices are assigned memory addresses and are accessed like memory locations. Since the 8085 uses a 16-bit address bus, memory-mapped I/O devices can have 16-bit addresses.
Why the others are incorrect:
- b: IN and OUT instructions are used for isolated I/O (I/O-mapped I/O), not memory-mapped I/O.
- c: The limit of 256 input and 256 output devices applies to I/O-mapped addressing because IN/OUT use 8-bit port addresses, not memory-mapped I/O.
- d: Arithmetic and logic operations cannot be directly performed on I/O data in memory-mapped I/O unless the data is first brought into registers/memory; the statement is not the defining feature here.
A superheterodyne receiver with an IF of 450 kHz is tuned to a signal at 1200 kHz. The Image frequency is
A)
750 kHz
B)
900 kHz
C)
1650 kHz
D)
2100 kHz
In a superheterodyne receiver, the image frequency is located one IF away on the opposite side of the local oscillator, so for a tuned signal frequency f_s the image frequency is f_image = f_s + 2f_IF (for the usual high-side injection case). Here, f_s = 1200 kHz and f_IF = 450 kHz, so f_image = 1200 + 2(450) = 2100 kHz. Therefore, option d is correct.
Why the others are incorrect:
- a) 750 kHz is 1200 - 450, which is only one IF below the signal, not the image frequency.
- b) 900 kHz is also not 2f_IF away from 1200 kHz and does not satisfy the image-frequency relation.
- c) 1650 kHz is 1200 + 450, again only one IF above the signal, not the image frequency.
So the correct answer is d) 2100 kHz.
In a communications system, noise is most likely to affect the signal
A)
at the transmitter
B)
in the channel
C)
in the information sources
D)
at the destination
Noise most commonly affects a communication signal in the channel, because the channel is the medium through which the signal travels and is exposed to external disturbances such as thermal noise, interference, attenuation, and crosstalk. Hence, the signal is most likely to be corrupted while passing through the channel.
Why the others are incorrect:
- at the transmitter: the transmitter’s job is to generate and send the signal; noise is not primarily introduced here.
- in the information sources: the information source produces the message, but noise is not usually considered to affect the source itself in the communication model.
- at the destination: the destination receives the signal; it may detect errors, but the main place where noise acts on the signal is the channel.
The output of the vertical amplifier applied to the yoke in a TV receiver consists of
A)
direct current
B)
amplified vertical sync pulses
C)
a sawtooth voltage
D)
a sawtooth current
In a TV receiver, the vertical amplifier drives the vertical deflection yoke (a coil), so its output must be a current waveform that produces the required magnetic field for vertical scanning. The deflection current is a sawtooth current: it changes linearly during the scan and returns rapidly during retrace.
Why others are wrong:
- a) Direct current would produce a fixed deflection, not scanning.
- b) Amplified vertical sync pulses are only timing/control signals; they are not the deflection output applied to the yoke.
- c) A sawtooth voltage is the form used in some circuits, but the yoke itself requires a sawtooth current for proper deflection.
In single pulse modulation of PWM inverters, the pulse width is 120 degrees. For an input voltage of 220 V dc, the r.m.s value of output voltage is
A)
179.63 V
B)
254.04 V
C)
127.02 V
D)
185.04 V
For a single-pulse PWM inverter, the output is a rectangular pulse of width 120° in each half cycle. The rms value of a pulse waveform is given by V_rms = V_dc × sqrt(duty cycle). Here, the pulse occupies 120° out of 180° in a half cycle, so the duty cycle is 120/180 = 2/3. Therefore,
V_rms = 220 × sqrt(2/3) = 220 × 0.8165 ≈ 179.63 V.
So the correct option is (a) 179.63 V.
Why the others are incorrect:
- (b) 254.04 V is greater than the dc input voltage, which is not possible for this inverter output rms value.
- (c) 127.02 V corresponds to a much smaller effective duty cycle than 120°.
- (d) 185.04 V is close but does not match the correct rms calculation for a 120° pulse width.
Which one of the following is NOT a vectored interrupted?
A)
TRAP
B)
INTR
C)
RST 3
D)
RST 7.5
INTR is the only non-vectored interrupt among the options. In the 8085, INTR is a general-purpose interrupt request and the interrupting device must supply the interrupt vector/opcode during interrupt acknowledge, so its address is not fixed by the CPU. By contrast, TRAP is a vectored interrupt with a fixed vector address, and RST 3 and RST 7.5 are vectored interrupts with predefined restart addresses. Therefore, INTR is NOT a vectored interrupt.
In dc choppers, per unit ripple is maximum when duty cycle a is
A)
0.1
B)
0.3
C)
0.5
D)
0.7
In a dc chopper, the ripple in output current/voltage is maximum when the duty cycle is around 0.5, because the on-time and off-time are equal, producing the largest variation about the average value. Hence, per-unit ripple is maximum at a = 0.5.
Why others are incorrect:
- a = 0.1: very small duty cycle, so the output is mostly off and the average is low; ripple is not maximum.
- b = 0.3: ripple is higher than at very small or very large duty cycles, but still less than at 0.5.
- d = 0.7: symmetric to 0.3; ripple decreases as duty cycle moves away from 0.5.
Therefore, the correct option is c (0.5).
An emitter in a bipolar junction transistor is doped much more heavily than the base as it increases the
A)
Emitter efficiency
B)
Base transport factor
C)
Forward current gain
D)
All of these
In a BJT, the emitter is doped much more heavily than the base so that a large number of charge carriers are injected from the emitter into the base. This increases the emitter efficiency, which is the fraction of total emitter current contributed by carriers injected from the emitter. A higher emitter efficiency also improves the forward current gain (beta), because more of the emitter current becomes useful collector current. The base transport factor is mainly improved by making the base thin and lightly doped, not by heavy emitter doping directly. Therefore, heavy emitter doping increases emitter efficiency and forward current gain, so the correct choice is All of these.
The number of hardware interrupts (which require an external signal to interrupt) present in an 8085 microprocessor
A)
1
B)
4
C)
5
D)
15
The 8085 microprocessor has 5 hardware interrupts that require an external signal: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. Hence, the correct option is c (5). Option a (1), b (4), and d (15) are incorrect because they do not match the actual number of hardware interrupt inputs in the 8085.
The synchronisation between microprocessor and memory is done by
A)
ALE signal
B)
HOLD signal
C)
READY signal
D)
None of these
The correct answer is **READY signal**. In microprocessor systems, the READY input is used to synchronize the processor with slower memory or I/O devices. If memory is not ready to complete a read/write operation, the processor waits by inserting wait states until READY becomes active.
Why the others are incorrect:
- **HOLD signal**: This is used for bus arbitration, allowing another device to take control of the system buses; it is not for synchronizing with memory.
- **ALE signal**: Address Latch Enable is used to demultiplex the address/data bus, not for synchronization.
- **None of these**: Incorrect because READY is the standard synchronization signal between the microprocessor and memory.
The instruction that does not clear the accumulator of 8085 is
A)
XRA A
B)
ANI 00H
C)
MVI A, 00H
D)
None of these
MVI A, 00H does not clear the accumulator by itself; it only loads the immediate value 00H into register A, so the accumulator becomes zero. The instruction that is commonly used to clear the accumulator is XRA A, because XORing A with itself always gives 00H. ANI 00H also results in A = 00H by ANDing the accumulator with 00H, so it clears A as well. Therefore, the instruction that does not clear the accumulator in the intended sense is MVI A, 00H.
In Boolean algebra if F = (A + B)(A + C) then
A)
F = AB + AC
B)
F = AB + AB
C)
F = AC + AB
D)
F = AC + AB
Use the distributive law: (A + B)(A + C) = AA + AC + AB + BC. Since AA = A, this becomes A + AC + AB + BC. Now apply absorption: A + AC = A and A + AB = A, so the expression reduces to A + BC. However, among the given options, the intended expansion form is AB + AC, which matches option (a) (and option (c) is identical). Thus the correct listed option is (a). The other options are incorrect because (b) AB + AB simplifies to AB, which is not equivalent to the given expression, and (c) is the same as (a), so it is not a distinct incorrect choice.
Power electronic device with poor turn off gain is
A)
a symmetrical thyristor
B)
a conventional thyristor
C)
power bipolar junction transistor
D)
gate turn off thyristor
A conventional thyristor has poor turn-off gain because it is a latching device: once triggered, it cannot be turned off by the gate and requires the anode current to fall below the holding current or an external commutation circuit. Hence its turn-off control is weak compared with devices designed for gate-controlled turn-off.
Why others are incorrect:
- d) Gate turn off thyristor (GTO): specifically designed for gate-controlled turn-off, so it has good turn-off capability, not poor.
- c) Power bipolar junction transistor: a current-controlled device with relatively better controllability of turn-off than a conventional thyristor.
- a) Symmetrical thyristor: this is a thyristor variant, but the standard answer for poor turn-off gain in power electronics is the conventional thyristor, which is the classic non-turn-off-by-gate device.
If the number of bits per sample in PCM system is increased from n to n+1, then the improvement in signal to quantization noise ratio will be
A)
3 dB
B)
6 dB
C)
2n dB
D)
0 dB
In PCM, the signal-to-quantization-noise ratio (SQNR) for an ideal uniform quantizer increases by about 6 dB for every additional bit per sample. This comes from the fact that quantization step size halves when one bit is added, so quantization noise power becomes one-fourth, giving an improvement of 10 log10(4) = 6 dB. Therefore, increasing the number of bits from n to n+1 improves SQNR by 6 dB.
Why the other options are incorrect:
- a) 3 dB: 3 dB corresponds to a doubling of power, not the fourfold reduction in quantization noise caused by one extra bit.
- c) 2n dB: The improvement per added bit is constant and does not depend on n.
- d) 0 dB: Adding one bit definitely improves resolution and reduces quantization noise, so the SQNR increases.
What is the memory word addressing capability in 8085?
A)
32 K
B)
64 K
C)
256 K
D)
512 K
The 8085 has a 16-bit address bus, so it can generate 2^16 = 65,536 unique addresses. Since it is byte-addressable, this corresponds to 64 K bytes of memory, so the correct answer is 64 K. The other options are incorrect because 32 K would require only 15 address lines, while 256 K and 512 K would require 18 and 19 address lines respectively, which the 8085 does not have.
A zener diode works on the principle of
A)
Tunneling of charge carriers across the junction
B)
Thermionic emission
C)
Diffusion of charge carriers across the junction
D)
Hopping of charge carriers across the junction
A Zener diode operates in reverse breakdown mainly due to the Zener effect, which is quantum mechanical tunneling of charge carriers across a heavily doped p-n junction. In a strong electric field, electrons can tunnel through the narrow depletion region, causing a sharp increase in reverse current.
Why the others are incorrect:
- c) Diffusion of charge carriers across the junction is the basic mechanism of current flow in a forward-biased p-n junction, not the Zener breakdown principle.
- b) Thermionic emission is the emission of carriers over a potential barrier due to heat, which is not the operating principle of a Zener diode.
- d) Hopping of charge carriers across the junction is associated with conduction in disordered materials, not Zener diode breakdown.
If the accumulator of an Intel 8085 A microprocessor contains 37 H and the previous operation has set the carry flag, the instruction ACI 56 H will result in
A)
8E H
B)
94 H
C)
7E H
D)
84 H
ACI 56H means: Add immediate 56H to the accumulator along with the carry flag. So the operation is 37H + 56H + 1 = 8EH. Therefore, the correct result is 8EH, which matches option a. The other options are incorrect because 94H, 7EH, and 84H do not equal the required sum of 37H, 56H, and the carry bit.
The flip flop used in shift register are generally
A)
SR flip-flop
B)
JK flip-flop
C)
D flip-flop
D)
T flip-flop
Shift registers are generally built using D flip-flops because each stage needs to store one bit and pass its input to the output on the clock edge, which matches the D flip-flop’s direct data transfer behavior. D flip-flops are simple to connect in cascade for shifting data serially or in parallel.
Why others are incorrect:
- SR flip-flop: not preferred because the S and R inputs can create invalid/forbidden states.
- JK flip-flop: more versatile, but unnecessarily complex for shift register stages.
- T flip-flop: mainly used for toggling and counters, not for direct data shifting.