Past Questions — 2024

A Multiplexer (MUX) is a combinational circuit that selects one of several input signals and forwards the selected input into a single line. To achieve this, the internal logic is structured as follows: 1. **AND Stage**: Each input line is connected to an AND gate along with a unique combination of select lines. Only one AND gate will have all its inputs high (1) for a given select line combination, effectively 'selecting' that specific input. 2. **OR Stage**: The outputs of all these AND gates are fed into a single OR gate. Since only one AND gate is active at a time, the OR gate simply passes the value of the selected input to the final output. Therefore, the fundamental logic implementation of a multiplexer is an AND-OR configuration (Sum of Products form).

A NOT gate is a basic logic gate that performs logical negation. It takes one input and produces the opposite logic level as output. In binary terms: if the input is '1', the output is '0'; if the input is '0', the output is '1'. When a signal is applied 'serially', it means each bit of the sequence is processed individually in the order it arrives. Given input signal A = 1 1 0 0 1: 1. First bit '1' becomes '0' 2. Second bit '1' becomes '0' 3. Third bit '0' becomes '1' 4. Fourth bit '0' becomes '1' 5. Fifth bit '1' becomes '0' Resulting output sequence: 00110. Comparing this to the options: - Option a (111) is incorrect as it changes the length of the signal. - Option b (110) is incorrect as it changes the length of the signal. - Option c (00110) is the exact logical inverse of the input. - Option d (11001) is incorrect as it is identical to the input (buffer behavior, not NOT gate).

A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) consists of a gate electrode separated from the semiconductor channel by a thin layer of insulating silicon dioxide (SiO2). This structure inherently forms a capacitor (the gate capacitance). By varying the voltage applied to the gate (Vgs), the charge carrier density in the channel is modified, effectively changing the capacitance of the device. Because the control mechanism is the voltage applied to the gate, and the physical structure acts as a capacitor, the MOSFET can be modeled or used as a voltage-controlled capacitor (often referred to as a varactor effect in specific contexts or used in switched-capacitor circuits). Comparing the options: - (a) Current controlled capacitor: Incorrect, as MOSFETs are voltage-driven devices, not current-driven. - (b) Voltage controlled capacitor: Correct, due to the insulated gate structure and the dependence of capacitance on gate voltage. - (c) Current controlled inductor: Incorrect, MOSFETs do not possess inherent inductance and are not current-controlled. - (d) Voltage controlled inductor: Incorrect, MOSFETs are not inductive devices.

A chopper is a static device that converts fixed DC input voltage to a variable DC output voltage. The average output voltage (Vout) of a chopper is given by the formula: Vout = D * Vin, where 'D' is the duty cycle and 'Vin' is the input voltage. The duty cycle (D) is defined as the ratio of the ON-time (Ton) to the total switching period (T), where T = Ton + Toff. By varying the duty cycle (changing the ratio of Ton to Toff), the average load voltage can be precisely controlled. Why other options are incorrect: - b. Firing angle: This term is primarily associated with Phase-Controlled Rectifiers (using SCRs) to control AC to DC conversion, not DC to DC choppers. - c. Reactor position: While inductors (reactors) are used in choppers to smooth the current ripple, their 'position' does not control the average output voltage. - d. Extinction angle: This is a parameter related to the commutation process in thyristors/SCRs, specifically in line-commutated converters, and does not determine the output voltage of a chopper.

In communication systems, modulation is the process of varying one or more properties of a high-frequency periodic waveform (the carrier signal) with a modulating signal (the message signal) that contains the information to be transmitted. 1. The 'Carrier' is a high-frequency sinusoidal signal. By definition, before it is modulated, it is a stable wave with a constant amplitude, constant frequency, and constant phase. 2. Option (a) describes the 'Modulating Signal' or 'Baseband Signal' (the information/speech). 3. Option (c) describes the 'Modulated Wave' (the result of the modulation process). 4. Option (d) describes the carrier *during* the process of modulation, but the carrier itself is the underlying stable reference signal that is being varied. Therefore, the carrier is fundamentally a voltage/signal with constant frequency, phase, or amplitude that serves as the vehicle for the information.

To determine the correct answer, we must compare the physical and operational characteristics of a Bipolar Junction Transistor (BJT) and a Power MOSFET: 1. **Conduction Loss**: - A **BJT** is a current-controlled device that operates in the saturation region during conduction. Its voltage drop across the collector-emitter junction (Vce(sat)) is relatively constant and low, regardless of the current level. This makes it more efficient for high-current applications, resulting in **lower conduction losses** compared to MOSFETs at high current levels. - A **Power MOSFET** acts as a voltage-controlled resistor (RDS(on)). The conduction loss is calculated as I² * RDS(on). As the current increases, the losses increase quadratically, making conduction losses higher than BJTs for high-power loads. 2. **Switching Loss**: - A **BJT** is a minority-carrier device. When it turns off, stored charges in the base region must be removed before the device can stop conducting (storage time). This slow transition increases the overlap of voltage and current during switching, leading to **higher switching losses**. - A **Power MOSFET** is a majority-carrier device. It does not suffer from minority carrier storage effects, allowing it to switch on and off much faster. This results in significantly lower switching losses. **Conclusion**: Compared to a Power MOSFET, a BJT has higher switching losses (due to storage time) but lower conduction losses (due to the constant saturation voltage drop).

To attenuate high frequencies, we need a component that allows high-frequency signals to bypass the load or be diverted to ground, effectively acting as a Low Pass Filter (LPF). 1. **Shunt Capacitance**: The capacitive reactance is given by $X_C = 1 / (2\pi fC)$. As frequency ($f$) increases, $X_C$ decreases. At very high frequencies, the capacitor acts as a short circuit to ground (shunt). This diverts high-frequency signals away from the output, resulting in attenuation. This is the fundamental principle of a shunt capacitor used in low-pass filtering. 2. **Series Capacitance**: A capacitor in series has high reactance at low frequencies and low reactance at high frequencies. Therefore, it blocks low frequencies and passes high frequencies (High Pass Filter), which is the opposite of the goal. 3. **Inductance**: An inductor in series would attenuate high frequencies (since $X_L = 2\pi fL$), but an inductor in shunt would pass high frequencies. Since the option just says 'inductance' without specifying the configuration, 'shunt capacitance' is the more standard and precise answer for a basic attenuation component in this context. 4. **Resistance**: A resistor provides a constant attenuation across all frequencies (frequency-independent), so it cannot specifically target high frequencies for attenuation.

The Early Effect, also known as Base-Width Modulation, occurs in a Bipolar Junction Transistor (BJT) when the collector-base junction is reverse-biased. As the reverse bias voltage ($V_{CB}$) increases, the depletion region at the collector-base junction widens. Since the collector is typically more heavily doped than the base, the depletion region extends significantly into the base region. This effectively reduces the 'effective width' of the base. A narrower base leads to a higher concentration gradient of minority carriers, which increases the collector current ($I_C$) for a given emitter-base voltage. Therefore, the Early effect is directly caused by the increase in the collector-base reverse bias. Why other options are incorrect: - Option (a) and (b): Fast turn-on and turn-off refer to switching speeds and transient responses, which are related to junction capacitances and charge storage, not the steady-state modulation of the base width. - Option (d): Large emitter-base forward bias increases the injection of carriers into the base, but it does not cause the narrowing of the base width associated with the Early effect.

Frequency Modulation (FM) can be generated using two primary methods: Direct and Indirect. 1. **Direct Method:** In this method, the frequency of the carrier oscillator is varied directly by the modulating signal. This is typically achieved by changing the capacitance of the oscillator circuit. Examples include the Varactor diode modulator, Reactance FET modulator, and Reactance bipolar transistor modulator. These methods are simple but often suffer from frequency instability. 2. **Indirect Method (Armstrong Method):** The indirect method generates FM by first creating a Narrowband FM (NBFM) signal and then using frequency multipliers to increase the frequency deviation and the carrier frequency to achieve Wideband FM (WBFM). The Armstrong modulator uses a phase modulator and a frequency multiplier to ensure high frequency stability, which is a significant advantage over direct methods. Therefore, options (a), (b), and (d) are all forms of direct FM generation, while the Armstrong modulator (c) is the standard indirect method.

A Zener diode is a specially doped P-N junction diode designed to operate reliably in the reverse breakdown region. While a standard diode is damaged by reverse breakdown, a Zener diode is engineered to have a precise, stable breakdown voltage (Zener voltage, Vz). Once the reverse bias reaches this breakdown point, the voltage across the diode remains almost constant even if the current through it increases significantly. This unique characteristic of the reverse-bias region is what allows it to be used as a voltage regulator to maintain a constant output voltage despite fluctuations in input voltage or load current. In the forward bias region, it behaves like a normal silicon diode and does not provide regulation.

An AND gate is a basic digital logic gate that implements logical conjunction. The fundamental rule for an AND gate is that the output is HIGH (1) if and only if ALL of its inputs are HIGH (1). If any single input is LOW (0), the output will be LOW (0). For a 3-input AND gate with inputs A, B, and C, the truth table logic is as follows: - Option a: A=0, B=0, C=0 → Output = 0 (LOW) - Option b: A=1, B=1, C=0 → Output = 0 (LOW because C is 0) - Option c: A=1, B=0, C=1 → Output = 0 (LOW because B is 0) - Option d: A=1, B=1, C=1 → Output = 1 (HIGH because all inputs are 1) Therefore, the output is HIGH only when A=1, B=1, and C=1.

In the context of microprocessor architecture, 'word length' typically refers to the size of the data the processor can handle in a single operation (the data bus width) and the size of its internal registers. For an 8-bit microprocessor (such as the Intel 8085), the internal data bus and the accumulator are 8 bits wide. However, the address bus (which determines the memory range the processor can access) is typically 16 bits wide to allow for a memory space of 64 KB (2^16 bytes). Therefore, the characteristic word lengths associated with an 8-bit microprocessor are 8 bits for data processing and 16 bits for memory addressing. Option (c) correctly identifies this standard pairing. Options (a), (b), and (d) include 32-bit or 64-bit lengths, which are characteristic of much more advanced 32-bit or 64-bit architectures, not 8-bit microprocessors.

A truth table for an n-input logic gate has 2^n possible input combinations. For a 4-input NAND gate, the number of entries (rows) is 2^4 = 16, so option d is correct. The other options are incorrect because 8 = 2^3, 32 = 2^5, and 6 is not a power of 2 and does not match the number of combinations for 4 inputs.

Oscillators are categorized based on the frequency range they can effectively generate. 1. **RC Oscillators (RC Phase Shift and Wien Bridge):** These use resistors and capacitors in their feedback networks. Due to the fact that capacitors have high impedance at low frequencies and very low impedance at high frequencies, RC circuits are primarily used for low-frequency applications, typically in the audio frequency (AF) range (from a few Hz up to about 1 MHz). They become unstable and inefficient in the megahertz (MHz) range. 2. **LC Oscillators (Hartley and Colpitts):** These use inductors (L) and capacitors (C) to form a resonant tank circuit. LC circuits are highly efficient at high frequencies because the resonance frequency is determined by $f = 1 / (2\pi\sqrt{LC})$. These are specifically designed for the Radio Frequency (RF) range, which spans from several hundred kHz into the megahertz (MHz) and gigahertz (GHz) ranges. Comparing the options: - **Option (a) RC phase shift:** Low frequency (AF). - **Option (b) Wien bridge:** Low frequency (AF). - **Option (c) Hartley:** High frequency (RF/MHz range). - **Option (d) Both (a) & (c):** Incorrect because RC phase shift is not suitable for MHz ranges. Therefore, the Hartley oscillator is the correct choice for frequencies in the megahertz range.

In digital electronics, a 'transparent' state refers to a condition where the output of a storage element changes immediately as the input changes, without waiting for a clock edge. While a standard D-flip-flop is edge-triggered (changing state only at the rising or falling edge of the clock), a D-latch (which is the building block of a flip-flop) is level-triggered. When the enable/clock signal of a D-latch is active (HIGH for an active-high latch), the output Q directly follows the input D. This behavior is termed 'transparency'. In the context of this question, 'transparency' specifically describes the state where the output tracks the input in real-time. Analysis of options: - Option (a) and (b) are incorrect because transparency is about the relationship between input and output, not the specific logic level (HIGH or LOW) of the output. - Option (c) is incorrect because the output follows the data input, not the clock signal itself. - Option (d) is correct as it defines the transparent mode where Q = D.

To find the 2's complement of a binary number, follow these two steps: Step 1: Find the 1's complement by inverting all the bits (changing 0s to 1s and 1s to 0s). Original Number: 10101011 1's Complement: 01010100 Step 2: Add 1 to the 1's complement result. 01010100 + 1 ---------- 01010101 Alternative Shortcut Method: Starting from the right (Least Significant Bit), keep all bits the same up to and including the first '1'. Then, invert all remaining bits to the left. Original: 1010101[1] (First '1' encountered at the end) Invert the rest: [0101010]1 Result: 01010101. Note: In the provided options, a, b, and d are identical (01010101). Option 'a' is selected as the first correct instance.

1. **Understand the Power Distribution in AM**: The total power ($P_t$) of a standard Amplitude Modulated (AM) wave is given by the formula: $P_t = P_c (1 + \frac{m^2}{2})$, where $P_c$ is the carrier power and $m$ is the modulation index. 2. **Given Data**: The modulation is 50%, so $m = 0.5$. 3. **Calculate Total Power ($P_t$)**: $P_t = P_c (1 + \frac{0.5^2}{2}) = P_c (1 + \frac{0.25}{2}) = P_c (1 + 0.125) = 1.125 P_c$. 4. **Identify Power Components**: - Carrier Power = $P_c$ - Total Sideband Power = $P_t - P_c = 0.125 P_c$ - Since there are two sidebands (USB and LSB) of equal power, the power in one sideband = $\frac{0.125 P_c}{2} = 0.0625 P_c$. 5. **Calculate Power of the Suppressed Signal**: The question states that the carrier AND one of the sidebands are suppressed. This describes a Single Sideband Suppressed Carrier (SSB-SC) system. - Power remaining = Power of one sideband = $0.0625 P_c$. - Power suppressed = $P_t - 0.0625 P_c = 1.125 P_c - 0.0625 P_c = 1.0625 P_c$. 6. **Calculate Percentage Saving**: Saving % = $\frac{\text{Power Suppressed}}{\text{Total Power}} \times 100$ Saving % = $\frac{1.0625 P_c}{1.125 P_c} \times 100 \approx 94.44%$. Therefore, the power saving is approximately 94.4%.

In digital electronics, a 'universal gate' is a gate that can be used to implement any other Boolean function (AND, OR, NOT, XOR, etc.) without the need for any other type of gate. 1. NAND Gate: By connecting the inputs of a NAND gate together, it acts as a NOT gate. By combining NAND gates, one can create AND and OR gates. Therefore, NAND is universal. 2. NOR Gate: Similarly, by connecting the inputs of a NOR gate together, it acts as a NOT gate. By combining NOR gates, one can create AND and OR gates. Therefore, NOR is universal. Evaluating the options: - Option (a): XOR and OR are not universal gates. - Option (b): OR, NOT, and XOR are not universal gates. - Option (c): While NOR and NAND are universal, XNOR is not. - Option (d): Both NOR and NAND are the recognized universal gates in digital logic.

A mod-N counter is a counter that has N distinct states. To determine the number of flip-flops (n) required to represent N states, we use the formula: 2^(n-1) < N ≤ 2^n. For a mod-16 counter, N = 16. Substituting this into the formula: 2^n ≥ 16. Since 2^4 = 16, the minimum number of flip-flops required is 4. Each flip-flop represents one binary bit; with 4 flip-flops, the counter can count from 0000 (0) to 1111 (15), totaling 16 unique states. Option (a) 5 flip-flops would allow for up to 32 states, (b) 6 would allow 64, and (c) 3 would only allow 8, which is insufficient for a mod-16 counter.

In a 3-phase full converter (also known as a 6-pulse converter), there are six thyristors (or diodes in an uncontrolled bridge) that conduct in a specific sequence. Each thyristor conducts for 120 degrees, and a new pulse is generated every 60 degrees of the input supply cycle. Since there are 6 such pulses within one complete cycle (360 degrees) of the supply frequency (f), the output voltage ripple or pulsation frequency is 6 times the supply frequency. Therefore, the ripple frequency is 6f. Comparison with other options: - Option (a) f: This would be the case for a single-phase half-wave rectifier. - Option (b) 2f: This is the ripple frequency for a single-phase full-wave converter. - Option (c) 3f: This is the ripple frequency for a 3-phase half-wave converter. - Option (d) 6f: Correct for a 3-phase full converter.

A Silicon Controlled Rectifier (SCR) is a four-layer semiconductor device consisting of alternating p-type and n-type materials (P-N-P-N structure). Because there are four layers of semiconductor material, there are exactly three P-N junctions formed at the interfaces: Junction J1 (between the first P and N layers), Junction J2 (between the second N and P layers), and Junction J3 (between the third P and fourth N layers). - Option (a) is correct because the P-N-P-N structure creates 3 junctions. - Option (b) is incorrect; a device with 2 junctions is typically a transistor (BJT). - Option (c) is incorrect; a device with 1 junction is a standard diode. - Option (d) is incorrect; a standard SCR does not have 4 junctions.

Reverse recovery current (I_rr) is the maximum current that flows in the reverse direction when a diode is switched from the forward-conducting state to the reverse-blocking state. 1. **Mechanism**: When a diode is forward-biased, minority carriers are stored in the depletion region and the neutral regions. When the bias is suddenly reversed, these stored charges must be removed before the diode can block current. This results in a transient reverse current. 2. **Dependence on Forward Current**: The amount of stored charge (Qrr) is directly proportional to the forward current (If) that was flowing just before the switching event. Since the reverse recovery current is the result of clearing these stored charges, its peak value is heavily dependent on the magnitude of the forward current. 3. **Analysis of other options**: - **Storage charge (b)**: While the reverse recovery *time* (trr) is closely linked to the storage charge, the *current* peak is specifically driven by the rate of change and the preceding forward current level. However, in most textbook contexts for this specific question phrasing, the forward current is the primary external control variable. - **Temperature (c)**: Temperature affects the carrier lifetime and leakage current, which influences the recovery time, but it is not the primary determinant of the reverse recovery current peak compared to the forward current. - **PIV (d)**: Peak Inverse Voltage (PIV) is the maximum voltage the diode can withstand in reverse bias; it does not determine the transient current flowing during the recovery phase.

In microprocessor architecture, registers are categorized into General Purpose Registers (GPRs) and Special Purpose Registers (SPRs). 1. **Program Counter (PC)**: This is a classic example of a Special Purpose Register. Its sole, dedicated function is to hold the memory address of the next instruction to be fetched and executed. It automatically increments after each fetch operation. Because it has a fixed, critical architectural role, it is 'special-purpose'. 2. **Instruction Register (IR)**: While the IR is also a specialized register (holding the current opcode), in many academic and competitive exam contexts for basic microprocessor courses, the Program Counter is the primary example used to define the concept of a special-purpose control register. However, technically, the IR is also special-purpose. But when compared to the Accumulator or Temporary registers, the PC is the most definitive answer for controlling the flow of execution. 3. **Accumulator**: The accumulator is often categorized as a general-purpose register (or a primary register) because it is used for a wide variety of arithmetic and logic operations. While it is 'special' in that it is the default operand, it serves as a general data workspace. 4. **Temporary Register**: These are used by the CPU internally to hold intermediate data during the execution of an instruction and are not accessible to the programmer, making them internal scratchpads rather than defined 'special-purpose' architectural registers like the PC. Therefore, the Program Counter is the most accurate answer as it performs a unique, non-data-storage function essential for the fetch-decode-execute cycle.

1. Initial State: Register A = 50H, Register B = 40H. 2. Instruction Analysis: The instruction 'MOV A, B' is a data transfer instruction used in microprocessors (such as the 8051 or 8085). The syntax 'MOV destination, source' means that the content of the source register is copied into the destination register. 3. Execution: In 'MOV A, B', register B is the source and register A is the destination. Therefore, the value in B (40H) is copied into A. 4. Final State: Register A now contains 40H. Since the MOV instruction is a non-destructive copy operation, the value in the source register B remains unchanged (40H). 5. Result: A = 40H, B = 40H. Comparison with options: - Option (a) 40H, 40H: Correct. - Option (b) 50H, 40H: Incorrect; this represents the state before the instruction was executed. - Option (c) 50H, 50H: Incorrect; this would happen if the instruction were 'MOV B, A'. - Option (d) 60H, 40H: Incorrect; no arithmetic addition occurred.

Step-by-step calculation: 1. **Identify the Circuit Topology**: The question describes a single-phase full-wave mid-point thyristor converter. In this configuration, a center-tapped transformer is used. The secondary winding is split into two equal halves by the center tap. 2. **Determine the Secondary Voltage**: The transformer rating is given as 230/200 V. This means the total secondary voltage (from end to end) is $V_s = 200\text{ V}$ (RMS). 3. **Calculate Voltage per Half-Winding**: Since it is a center-tapped transformer, the voltage across each half of the secondary winding is $V_{half} = \frac{V_s}{2} = \frac{200}{2} = 100\text{ V}$ (RMS). 4. **Determine Peak Inverse Voltage (PIV)**: In a mid-point converter, when one thyristor is conducting, the other thyristor is reverse-biased. The maximum reverse voltage (PIV) that the non-conducting thyristor must withstand is the peak value of the voltage across the half-winding. $$\text{PIV} = V_{peak} = \sqrt{2} \times V_{half}$ $$\text{PIV} = \sqrt{2} \times 100\text{ V} \approx 1.414 \times 100\text{ V} = 141.4\text{ V}$$ **Wait, let's re-evaluate the transformer notation**: In many engineering contexts for mid-point converters, the secondary voltage rating provided (200V) refers to the voltage of *each half* of the secondary relative to the center tap, or the total secondary. However, standard notation '230/200V' usually implies Primary/Secondary. If the total secondary is 200V, PIV is 141.4V. If the secondary is 200V *per side* (total 400V), PIV is 282.8V. Looking at the options: 141.4V (b) and 282.8V (d) are both present. In the context of typical competitive exam questions for this specific circuit, the 'secondary voltage' mentioned is often the voltage across the full secondary winding. However, if the intended answer is 282.8V, it implies the voltage across each half-winding is 200V. Let's check the standard PIV formula for a Mid-point converter: $\text{PIV} = 2V_m$ is for bridge converters in some contexts, but for Mid-point, it is simply the peak of the half-winding. If the secondary is 200V RMS total, PIV = 141.4V. If the secondary is 200V RMS per side, PIV = 282.8V. Given the options and common textbook problems for this specific exam pattern, the secondary voltage '200V' is frequently treated as the voltage of the half-winding ($V_s = 200\text{V}$ per side). Calculation: $\text{PIV} = 200 \times \sqrt{2} = 282.8\text{V}$.