← MES Jr. Grade
Past Questions — 2022
In high speed TDM, the channels are separated in the receiver employing :
A)
OR gate
B)
AND gate
C)
NAND gate
D)
NOR gate
In Time Division Multiplexing (TDM), multiple signals are transmitted over a single channel by dividing the time into slots. At the receiver end, a demultiplexer is used to separate these channels. In high-speed digital TDM, the demultiplexing process involves 'gating' the incoming composite signal. An AND gate acts as a synchronization switch: one input is the composite TDM signal, and the other input is a synchronization pulse (clock signal) specific to that channel. When the synchronization pulse is 'HIGH' (1), the AND gate allows the signal for that specific channel to pass through; when it is 'LOW' (0), the output is zero. This effectively 'picks out' the time slots belonging to a specific channel, separating it from the others. OR, NAND, and NOR gates do not perform this specific 'windowing' or 'gating' function required for signal separation in this context.
Which of the following is a non vectored hardware interrupt of 8085?
A)
TRAP
B)
RST 7.5
C)
INTR
D)
All of these
In the 8085 microprocessor, interrupts are categorized into two types: Vectored and Non-Vectored.
1. Vectored Interrupts: These are interrupts where the CPU automatically knows the address of the Interrupt Service Routine (ISR) to jump to. The 8085 has five vectored interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and RST 0.
- TRAP is the highest priority non-maskable vectored interrupt.
- RST 7.5 is a maskable vectored interrupt.
2. Non-Vectored Interrupts: These are interrupts where the CPU does not have a predefined address for the ISR. The external device providing the interrupt must provide the address of the ISR on the data bus during the interrupt acknowledge cycle.
- INTR (Interrupt Request) is the only non-vectored hardware interrupt in the 8085. When INTR is activated, the microprocessor responds by issuing an INTA (Interrupt Acknowledge) signal, and the external hardware must then place an instruction (usually a RST n or CALL instruction) on the data bus to tell the CPU where to go.
Therefore, TRAP and RST 7.5 are vectored, making INTR the correct choice.
In a single-phase full converter, the output voltage during overlap is equal to :
A)
zero
B)
source voltage
C)
source voltage minus the inductance drop
D)
none of these
In a single-phase full converter (fully controlled bridge), 'overlap' occurs due to the source inductance (L_s). During the overlap period, two thyristors in the same leg (or opposite legs depending on the commutation phase) are conducting simultaneously. Specifically, during the commutation interval, the outgoing thyristor and the incoming thyristor both conduct. Because they are connected in parallel across the AC source during this brief transition, the load is effectively connected directly across the AC source. Therefore, the output voltage during the overlap period is equal to the instantaneous source voltage (v_s).
- Option (a) is incorrect because the voltage does not drop to zero; it follows the source waveform.
- Option (c) is incorrect because the 'inductance drop' typically refers to the voltage drop across the source inductor that causes the delay in commutation, but the net voltage delivered to the load during the overlap period is the source voltage itself.
- Option (d) is incorrect as option (b) is the standard theoretical result for power electronics converters.
If a diode is connected in anti-parallel with a thyristor, then :
A)
both turn-off power loss and turn-off time decreases
B)
turn-off power loss and turn-off time increase
C)
turn-off power loss increase, but turn-off time decreases
D)
none of the above
In a thyristor (SCR), the turn-off process involves the removal of charge carriers from the junction. When a diode is connected in anti-parallel (reverse parallel) with the thyristor, it provides an alternative path for the current to flow during the commutation process. Specifically, during the turn-off phase, the anti-parallel diode allows the reverse recovery current to flow more efficiently and helps in faster removal of the stored charges from the thyristor's gate and junctions. This reduces the 'turn-off time' (tc). Because the device spends less time in the transition region where both voltage and current are present, the energy dissipated during the turn-off process is reduced, thereby decreasing the 'turn-off power loss'. Therefore, both the turn-off time and the associated power loss decrease.
Each diode of a 3-phase half-wave diode rectifier conducts for :
A)
60o
B)
120o
C)
180o
D)
90o
In a 3-phase half-wave rectifier, there are three diodes, each connected to one phase of the 3-phase supply. The circuit is designed such that the diode connected to the phase with the highest instantaneous voltage conducts, while the others are reverse-biased.
1. The phase voltages are displaced by 120° from each other.
2. A specific diode starts conducting when its phase voltage becomes the most positive among the three phases. This occurs at 30° relative to the phase's own zero-crossing (or -30° relative to the peak).
3. The diode continues to conduct until the next phase voltage exceeds its own voltage.
4. Since the phases are separated by 120°, each diode conducts for exactly one-third of the total cycle (360° / 3 = 120°).
Therefore, the conduction angle for each diode is 120°.
Comparison with other options:
- 60°: Incorrect; this is not the conduction period for a standard half-wave rectifier.
- 180°: Incorrect; this is the conduction angle for diodes in a single-phase full-wave bridge rectifier.
- 90°: Incorrect; this does not correspond to the symmetry of a 3-phase system.
Turn-on and turn-off times of transistor depend on :
A)
static characteristic
B)
junction capacitances
C)
current gain
D)
voltage injection
The turn-on and turn-off times of a transistor (switching speed) are primarily determined by the time it takes to charge and discharge the internal capacitances of the device. In a Bipolar Junction Transistor (BJT), these are the depletion region capacitances of the emitter-base and collector-base junctions.
1. **Turn-on time**: This involves charging the junction capacitances to the required threshold voltage to move the transistor from the cutoff region to the saturation region.
2. **Turn-off time**: This is dominated by the 'storage time,' which is the time required to remove the excess minority carriers stored in the base region and discharge the junction capacitances to move the transistor from saturation back to cutoff.
Why other options are incorrect:
- **Static characteristics (a)**: These describe the DC behavior (like V-I curves) and do not account for the time-dependent (transient) behavior of the device.
- **Current gain (c)**: While current gain ($\beta$) affects the amount of current flowing, it does not directly dictate the speed of the charging/discharging process of the junctions.
- **Voltage injection (d)**: This is not a standard term used to define the intrinsic switching speed of a transistor; the speed is a property of the device's physical construction and capacitance.
In a 3-phase controlled bridge rectifier, with an increase of overlap angle the output DC voltage :
A)
decreases
B)
increases
C)
does not change
D)
depends upon load inductance
In a 3-phase controlled bridge rectifier, the 'overlap angle' (denoted as μ) occurs due to the source inductance (commutation inductance). In an ideal scenario (zero source inductance), the current transfers instantaneously from one thyristor to the next. However, in practical circuits, the source inductance prevents the current from changing instantaneously. During the overlap period, two thyristors in the same group are conducting simultaneously. This creates a short-circuit path across the DC output for a brief duration, effectively averaging the output voltage between the outgoing and incoming phases. The mathematical expression for the average output voltage (Vdc) of a 3-phase fully controlled bridge rectifier considering overlap is: Vdc = (3√3 Vm / π) * [cos(α) - (μ/2π)sin(α)] (approximately, or more precisely involving the integral of the voltage during overlap). As the overlap angle μ increases, the voltage drop across the source inductance increases, which reduces the average DC output voltage. Therefore, an increase in the overlap angle leads to a decrease in the output DC voltage.
The drawback of FM relative to AM is that :
A)
noise is very high for high modulation frequencies
B)
larger bandwidth is required
C)
higher modulating power is required
D)
higher output power is required
To determine the drawback of Frequency Modulation (FM) relative to Amplitude Modulation (AM), we compare their fundamental characteristics:
1. **Bandwidth**: In AM, the bandwidth is simply twice the highest modulating frequency (BW = 2fm). In FM, the bandwidth is determined by Carson's Rule (BW ≈ 2(Δf + fm)), where Δf is the frequency deviation. Because Δf is typically much larger than the modulating frequency to achieve a good signal-to-noise ratio, FM requires a significantly larger portion of the frequency spectrum than AM. This is the primary technical drawback of FM.
2. **Noise Performance**: FM is actually superior to AM in terms of noise. Most noise (like atmospheric or electrical noise) affects the amplitude of a signal. Since FM carries information in the frequency variations and uses 'limiters' to clip amplitude spikes, it is much more resistant to noise than AM. Therefore, option (a) is incorrect.
3. **Power Requirements**: In FM, the amplitude of the carrier remains constant regardless of the modulation index. This means the transmitted power is constant and does not increase with modulation depth, unlike AM where power increases with the modulation index. Therefore, options (c) and (d) are incorrect as FM does not inherently require 'higher' power to operate; in fact, it is more power-efficient in terms of signal quality.
Conclusion: The trade-off for the superior noise immunity and audio quality of FM is the requirement for a much larger bandwidth.
Which of the following amplifier operations has the highest efficiency?
A)
Class A amplifier
B)
Class B amplifier
C)
Class C amplifier
D)
None of these
Efficiency in power amplifiers is defined as the ratio of the AC power delivered to the load to the DC power drawn from the supply.
1. **Class A Amplifier**: The transistor conducts for the full 360° of the input cycle. Because it draws current even when there is no input signal, it has the lowest efficiency. The maximum theoretical efficiency for a series-fed Class A amplifier is 25%, and 50% for a transformer-coupled one.
2. **Class B Amplifier**: The transistor conducts for only 180° (half) of the input cycle. This significantly reduces power wastage. The maximum theoretical efficiency is approximately 78.5%.
3. **Class C Amplifier**: The transistor conducts for less than 180° (a small fraction) of the input cycle. Because the conduction angle is very small, the DC power consumption is minimized while the output is maintained using a tuned LC resonant circuit. This allows Class C amplifiers to achieve the highest theoretical efficiency, often exceeding 80% and reaching up to 90% or more.
Comparing the three, Class C is the most efficient, although it introduces significant distortion and is primarily used in RF applications.
The disadvantage of FM over AM is that
A)
noise is very high for high frequency signals
B)
larger bandwidth is required
C)
high modulating power is required
D)
high output power is required
To determine the disadvantage of Frequency Modulation (FM) compared to Amplitude Modulation (AM), we must compare their fundamental characteristics:
1. **Bandwidth**: In AM, the bandwidth is simply twice the highest modulating frequency (BW = 2fm). In FM, the bandwidth is determined by Carson's Rule (BW ≈ 2(Δf + fm)), where Δf is the frequency deviation. Because Δf is typically much larger than the modulating frequency to achieve a good signal-to-noise ratio, FM requires a significantly larger bandwidth than AM. This is the primary disadvantage of FM.
2. **Noise (Option a)**: This is incorrect. One of the main advantages of FM over AM is its superior noise immunity. Since noise primarily affects the amplitude of a signal, an FM receiver can use a 'limiter' to clip amplitude variations without losing the frequency-encoded information.
3. **Modulating Power (Option c)**: This is incorrect. The power required for modulation is not the defining disadvantage of FM; rather, it is the complexity of the circuitry.
4. **Output Power (Option d)**: This is incorrect. In FM, the transmitted power remains constant regardless of the modulation index, whereas in AM, the power varies with the modulation depth. FM does not inherently require 'higher' output power to function; it simply uses its power more efficiently to combat noise.
In a commutation circuit employed to turn-off an SCR, satisfactory turn-off is obtained when :
A)
Circuit turn-off time < device turn-off time
B)
Circuit turn-off time > device turn-off time
C)
Circuit time constant > device turn-off time
D)
Circuit time constant < device turn-off time
To successfully turn off a Silicon Controlled Rectifier (SCR), two conditions must be met: first, the current must be reduced below the holding current, and second, a reverse voltage must be applied across the device for a sufficient duration to allow the internal charge carriers to recombine.
1. **Device Turn-off Time (tc):** This is a characteristic property of the SCR. It is the minimum time required for the device to regain its forward-blocking capability after the current has dropped to zero.
2. **Circuit Turn-off Time (tc'):** This is the time provided by the external commutation circuit during which the SCR is reverse-biased.
For a satisfactory turn-off (to prevent the device from accidentally re-triggering or failing to block forward current), the time provided by the circuit (tc') must be greater than the time required by the device (tc). If tc' < tc, the device will not have fully recovered its blocking state before the forward voltage is reapplied, leading to an immediate conduction (failure to turn off). Therefore, the condition for successful commutation is: Circuit turn-off time > device turn-off time.
How many flags do 8085 microprocessor has?
A)
5
B)
9
C)
11
D)
None of these
The 8085 microprocessor has a 8-bit Flag Register (also known as the Program Status Word). Although the register is 8 bits wide, only 5 bits are used as status flags to indicate the results of arithmetic and logical operations. These five flags are:
1. Carry Flag (CY): Set if there is a carry out from the most significant bit (MSB).
2. Parity Flag (P): Set if the result contains an even number of 1s.
3. Auxiliary Carry Flag (AC): Set if there is a carry from bit D3 to D4 (used for BCD arithmetic).
4. Zero Flag (Z): Set if the result of an operation is zero.
5. Sign Flag (S): Set if the MSB of the result is 1 (indicating a negative number in 2's complement).
The other 3 bits in the flag register are undefined/unused. Therefore, the correct number of flags is 5.
In a three phase half-wave rectifier, each diode conducts for a duration of
A)
180o
B)
30o
C)
60o
D)
120o
In a three-phase half-wave rectifier, there are three diodes, each connected to one phase of the three-phase supply. The diodes conduct based on which phase has the highest instantaneous voltage.
1. The three-phase supply voltages are displaced by 120° from each other.
2. A diode will conduct only when its anode voltage is higher than the cathode voltage and higher than the voltages of the other two phases.
3. Each phase voltage remains the most positive for a duration of 120° (specifically, from 30° before its peak to 30° after its peak relative to the zero crossing, or more accurately, from the point where it intersects the previous phase to where it intersects the next phase).
4. Therefore, each diode conducts for exactly 1/3 of the total cycle (360° / 3 = 120°).
Comparison with other options:
- 180° is the conduction angle for diodes in a single-phase full-wave rectifier or a three-phase full-wave bridge rectifier.
- 60° and 30° do not correspond to the standard conduction intervals of a half-wave three-phase configuration.
In differential PCM, Each word indicates :
A)
difference between a sample amplitude and a reference signal
B)
difference in amplitude between a sample and the previous sample
C)
addition of a sample amplitude and a reference signal
D)
addition of amplitude of a sample and the previous sample
Differential Pulse Code Modulation (DPCM) is a signal compression technique used in communication systems. In standard PCM, the absolute value of each sample is quantized and transmitted. However, in most signals (like speech or audio), successive samples are highly correlated, meaning they don't change drastically from one to the next. DPCM takes advantage of this redundancy by transmitting only the difference between the current sample and a predicted value (usually based on the previous sample).
Step-by-step reasoning:
1. The system predicts the value of the current sample based on previous samples.
2. The actual sample value is compared to this prediction.
3. The difference (error signal) is calculated: Difference = Current Sample - Predicted Value.
4. This difference is quantized and transmitted as the 'word'.
5. Since the prediction is typically based on the previous sample, the word effectively represents the difference in amplitude between the current sample and the previous one.
Analysis of options:
- Option (a) is incorrect because it refers to a general 'reference signal' rather than the specific temporal correlation used in DPCM.
- Option (b) is correct as it accurately describes the differential nature of DPCM.
- Option (c) and (d) are incorrect because DPCM relies on subtraction (differencing) to reduce the dynamic range of the signal, not addition.
To construct a 512 K x 8 memory , the number of 32 K x 4 memory circuit required is :
A)
16
B)
32
C)
8
D)
64
To determine the number of smaller memory chips required to construct a larger memory array, we compare the total capacity of the target memory with the capacity of a single available chip.
1. **Target Memory Capacity**:
The target memory is 512 K x 8.
Total bits = (512 * 1024) words * 8 bits/word = 4,194,304 bits.
2. **Available Chip Capacity**:
The available chip is 32 K x 4.
Total bits = (32 * 1024) words * 4 bits/word = 131,072 bits.
3. **Calculation of Number of Chips**:
Number of chips = (Total Target Capacity) / (Capacity of one chip)
Number of chips = (512 K * 8) / (32 K * 4)
Number of chips = (512 / 32) * (8 / 4)
Number of chips = 16 * 2 = 32.
Alternatively, looking at it by dimensions:
- To increase the word capacity from 32K to 512K, we need 512/32 = 16 rows of chips.
- To increase the word size (bit width) from 4 bits to 8 bits, we need 8/4 = 2 columns of chips.
- Total chips = 16 rows * 2 columns = 32 chips.
What is the duty cycle of the output of an astable multivibrator?
A)
50%
B)
100%
C)
75%
D)
55%
An astable multivibrator is a free-running oscillator that switches between two states without any external trigger. The duty cycle is defined as the ratio of the 'ON' time (T_on) to the total period (T = T_on + T_off). In a standard, symmetric astable multivibrator circuit (where the RC time constants for both charging and discharging paths are identical), the time spent in the high state is equal to the time spent in the low state. Therefore, T_on = T_off, and the duty cycle is (T_on / (T_on + T_off)) * 100% = (T_on / 2T_on) * 100% = 50%. While it is possible to design an astable multivibrator with a variable duty cycle by using different resistor or capacitor values, in the context of general theoretical exam questions where no specific component values are provided, the 'ideal' or 'standard' astable multivibrator is assumed to be symmetric, resulting in a 50% duty cycle.
At saturation, which of these is not true for a BJT?
A)
The collector current IC cannot increase further
B)
The base current IB, cannot increase further
C)
The collector-to-emitter voltage, VCE is due to the non-zero internal resistance of BJT
D)
VCE(saturation) is the minimum voltage drop between C and E
In a Bipolar Junction Transistor (BJT), saturation occurs when both the base-emitter junction and the base-collector junction are forward-biased.
1. **Option (a) is true**: In saturation, the collector current (IC) is limited by the external circuit (the load resistor and supply voltage). Even if the base current is increased, IC cannot increase further because it has reached its maximum possible value for the given circuit configuration.
2. **Option (b) is NOT true**: This is the correct answer. Even after the transistor reaches saturation, the base current (IB) can continue to increase if the base-emitter voltage is increased. The transistor remains in saturation, but IB continues to rise without causing a corresponding increase in IC. This is why the gain beta (β = IC/IB) drops significantly in the saturation region.
3. **Option (c) is true**: Ideally, VCE would be 0V in saturation, but due to the internal bulk resistance of the semiconductor material and the junctions, a small non-zero voltage (VCE(sat)) remains.
4. **Option (d) is true**: VCE(sat) represents the minimum voltage drop across the collector-emitter terminals when the transistor is acting as a closed switch.
In a waveguide, the evanescent modes are said to occur if :
A)
Phase constant is zero
B)
Phase constant is real
C)
Phase constant is imaginary
D)
The signal has constant frequency
In a waveguide, the propagation constant (gamma) is given by γ = α + jβ, where α is the attenuation constant and β is the phase constant. The relationship between the operating frequency (ω), the cutoff frequency (ωc), and the propagation constant is defined by the equation: β = √(k^2 - k_c^2), where k = ω/v is the wavenumber and k_c is the cutoff wavenumber.
1. Propagating Modes: When the operating frequency is above the cutoff frequency (ω > ωc), the term under the square root is positive. Thus, β is real, and the wave propagates through the waveguide without attenuation (in an ideal case).
2. Evanescent Modes: When the operating frequency is below the cutoff frequency (ω < ωc), the term under the square root becomes negative. This makes the phase constant β purely imaginary (β = jα).
When β is imaginary, the propagation factor e^(-jβz) becomes e^(-αz), which represents an exponential decay of the field amplitude along the axis of the waveguide rather than a traveling wave. These non-propagating, decaying fields are called evanescent modes. Therefore, evanescent modes occur when the phase constant is imaginary.
The highest noise margin is offered by
A)
TTL
B)
ECL
C)
IIL
D)
CMOS
Noise margin is the maximum noise voltage that can be added to an input signal without changing the output state of the logic gate. It is essentially the difference between the maximum output voltage of a driving gate and the minimum input voltage required by the receiving gate to recognize the logic level.
1. **CMOS (Complementary Metal-Oxide-Semiconductor):** CMOS technology uses both PMOS and NMOS transistors. Its logic levels are typically rail-to-rail (from 0V to VDD). Because the output swings fully from ground to the supply voltage, the gap between the output voltage and the switching threshold is very large, resulting in the highest noise margin among the listed logic families.
2. **TTL (Transistor-Transistor Logic):** TTL uses bipolar transistors. Its logic levels are more constrained (e.g., V_OH is typically lower than VDD), leading to a significantly lower noise margin compared to CMOS.
3. **ECL (Emitter-Coupled Logic):** ECL is designed for high speed. It operates in the non-saturated region, meaning the voltage swing between logic '0' and logic '1' is very small (typically around 0.8V). Because the swing is so small, the noise margin is the lowest among all these families.
4. **IIL (Injection-saturating Input Logic):** IIL has noise margins that are generally lower than CMOS and comparable to or slightly better than some TTL variants, but it cannot compete with the rail-to-rail swing of CMOS.
Therefore, CMOS offers the highest noise immunity.
The depth of penetration of a wave in a lossy dielectric increases with increasing :
A)
Conductivity
B)
Permeability
C)
Wavelength
D)
Permittivity
The depth of penetration (also known as skin depth, δ) is the distance over which the amplitude of an electromagnetic wave decreases to 1/e (approximately 37%) of its original value as it penetrates a lossy medium.
For a good conductor or a lossy dielectric, the skin depth is given by the formula:
δ = 1 / α
In the case of a good conductor (where conductivity σ >> ωε), the formula simplifies to:
δ = √(2 / (ωμσ)) = √(1 / (π f μ σ))
Where:
- ω = angular frequency (2πf)
- μ = permeability
- σ = conductivity
- f = frequency
Analysis of the options:
1. Conductivity (σ): Since δ is inversely proportional to √σ, increasing conductivity decreases the depth of penetration.
2. Permeability (μ): Since δ is inversely proportional to √μ, increasing permeability decreases the depth of penetration.
3. Wavelength (λ): Wavelength is inversely proportional to frequency (λ = v/f). Since δ is inversely proportional to √f, it is directly proportional to √λ. Therefore, increasing the wavelength (which means decreasing the frequency) increases the depth of penetration.
4. Permittivity (ε): In a lossy dielectric, the attenuation constant α depends on permittivity. Generally, increasing permittivity increases the attenuation, thereby decreasing the penetration depth.
Therefore, the depth of penetration increases as the wavelength increases.
For a lossy transmission line, the characteristics impedance does not depend on :
A)
Frequency of operation on the line
B)
Load of the line
C)
Conductivity of the conductor
D)
Inductance of the line
The characteristic impedance (Z₀) of a transmission line is an intrinsic property of the line itself, determined by its physical construction and the materials used. For a lossy transmission line, the formula for characteristic impedance is given by: Z₀ = √( (R + jωL) / (G + jωC) ), where R is the resistance per unit length, ω is the angular frequency, L is the inductance per unit length, G is the conductance per unit length, and C is the capacitance per unit length.
Analyzing the options:
1. Frequency of operation (ω): Z₀ depends on frequency because ω appears in both the numerator and denominator.
2. Load of the line: Z₀ is the impedance the line 'presents' to a source if the line is infinitely long or terminated in a load equal to Z₀. The actual load connected at the end of the line affects the reflection coefficient and the voltage/current distribution, but it does NOT change the intrinsic characteristic impedance of the line itself.
3. Conductivity of the conductor: Conductivity affects the resistance (R) and conductance (G), both of which are variables in the Z₀ formula.
4. Inductance of the line (L): L is a direct variable in the Z₀ formula.
Therefore, the characteristic impedance is independent of the load connected to the line.
A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by and one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles.
A)
an AND gate
B)
an OR gate
C)
an XOR gate
D)
a NAND gate
Step-by-step reasoning:
1. **Analyze the Requirement**: The problem describes a standard staircase wiring system. The key requirement is that the state of the bulb (ON/OFF) can be changed by toggling either switch, regardless of the position of the other switch.
2. **Truth Table Construction**:
Let S1 be the switch at the ground floor and S2 be the switch at the first floor. Let L be the state of the bulb (0 = OFF, 1 = ON).
- If both switches are in the same position (both DOWN or both UP), let's assume the light is OFF: (0,0) -> 0 and (1,1) -> 0.
- If the switches are in opposite positions, the circuit is completed and the light is ON: (0,1) -> 1 and (1,0) -> 1.
3. **Matching with Logic Gates**:
- **AND gate**: Output is 1 only if both inputs are 1. (Does not match).
- **OR gate**: Output is 1 if any input is 1. (Does not match, as (1,1) would be 1).
- **XOR (Exclusive OR) gate**: Output is 1 if and only if the inputs are different. This perfectly matches the truth table: 0 XOR 0 = 0; 0 XOR 1 = 1; 1 XOR 0 = 1; 1 XOR 1 = 0.
- **NAND gate**: Output is 0 only if both inputs are 1. (Does not match).
4. **Conclusion**: The behavior where changing the state of any single input flips the output state is the defining characteristic of an XOR gate (or an XNOR gate, but XOR is the standard representation for this logic in multiple-choice questions of this type).
Which one of the following is not correct Maxwell equation?
A)
∇ × H = J + dD/dt
B)
∇ × E = -dB/dt
C)
∇ × D = ρ
D)
∇ × B = 0
To identify the incorrect Maxwell equation, let's review the four fundamental Maxwell's equations in differential form:
1. Gauss's Law for Electricity: ∇ · D = ρ (The divergence of the electric flux density is equal to the volume charge density).
2. Gauss's Law for Magnetism: ∇ · B = 0 (The divergence of the magnetic flux density is zero, meaning there are no magnetic monopoles).
3. Faraday's Law of Induction: ∇ × E = -∂B/∂t (The curl of the electric field is equal to the negative rate of change of the magnetic flux density).
4. Ampere-Maxwell Law: ∇ × H = J + ∂D/∂t (The curl of the magnetic field intensity is equal to the sum of the conduction current density and the displacement current density).
Evaluating the options:
- Option (a): ∇ × H = J + dD/dt is the correct Ampere-Maxwell Law.
- Option (b): ∇ × E = -dB/dt is the correct Faraday's Law.
- Option (c): ∇ × D = ρ is INCORRECT. The correct equation is ∇ · D = ρ (Divergence, not Curl). The curl of D is not fundamentally defined as equal to charge density.
- Option (d): ∇ × B = 0 is not one of the four primary Maxwell equations in general form (the primary one is ∇ · B = 0). However, in the context of this specific multiple-choice question, Option (c) is a blatant mathematical error regarding the operator (Curl vs Divergence) for a fundamental law, making it the most 'incorrect' choice. Note: In static magnetic fields, ∇ × B = μ₀J, but ∇ · B = 0 is the universal law. Comparing (c) and (d), (c) replaces a divergence operator with a curl operator for Gauss's Law, which is a fundamental conceptual error.
A good current buffer has :
A)
Low-input impedance and low-output impedance
B)
Low-input impedance and high-output impedance
C)
High-input impedance and low-output impedance
D)
High-input impedance and high-output impedance
A buffer is designed to isolate a source from a load to prevent 'loading effects.' The requirements for a buffer depend on whether it is a Voltage Buffer or a Current Buffer:
1. **Voltage Buffer:** Its goal is to transfer voltage without loss. To avoid drawing current from the source, it needs High Input Impedance. To ensure the load receives the full voltage, it needs Low Output Impedance.
2. **Current Buffer:** Its goal is to transfer current from a source to a load without loss.
- **Input Impedance:** To ensure that the maximum amount of current from the source flows into the buffer (rather than through any parallel paths in the source circuit), the buffer must have a **Low Input Impedance**. This makes it act as a 'current sink'.
- **Output Impedance:** To ensure that the current is delivered efficiently to the load without being dropped across the internal resistance of the buffer itself, the buffer must have a **Low Output Impedance**. This ensures the current is pushed effectively into the load.
Therefore, a good current buffer requires both low input impedance and low output impedance.
What are the minimum number of 2 to 1 multiplexer required to generate a 2-input AND gate and 2-input EX-OR gate?
A)
1 and 2
B)
1 and 3
C)
1 and 1
D)
2 and 2
A 2-to-1 Multiplexer (MUX) implements the logic function: Y = S'I0 + SI1, where S is the select line and I0, I1 are the inputs.
1. For a 2-input AND gate (Y = A · B):
- Let A be the select line (S = A).
- If A = 0, Y must be 0 regardless of B. So, I0 = 0.
- If A = 1, Y must be equal to B. So, I1 = B.
- Equation: Y = A'(0) + A(B) = AB.
- Therefore, only 1 MUX is required for an AND gate.
2. For a 2-input XOR gate (Y = A ⊕ B = A'B + AB'):
- Let A be the select line (S = A).
- If A = 0, Y = B (since 0 ⊕ B = B). So, I0 = B.
- If A = 1, Y = B' (since 1 ⊕ B = B'). So, I1 = B'.
- To implement this, we need one MUX to perform the selection and another MUX to generate the complement of B (NOT gate).
- A NOT gate using a 2-to-1 MUX: S = B, I0 = 1, I1 = 0. Result = B'(1) + B(0) = B'.
- Total MUXes for XOR = 1 (for selection) + 1 (for NOT gate) = 2 MUXes.
Thus, the minimum number of 2-to-1 multiplexers required are 1 for the AND gate and 2 for the XOR gate.