← MES Jr. Grade
Past Questions
A linear time invariant, causal, continuous time system has a natural transfer function with sample poles at s = -2 and s = -4, and one sample zero at s = -1. A unit step u(t) is applied at the input of the system. A steady state output has constant value 1. The impulse response of this system is
A)
-4e^-2t u(t)
B)
-12e^-4t u(t)
C)
(-4e^-2t + 12e^-4t) u(t)
D)
-4e^-4t u(t)
Based on established principles in Electrical / Electronics Engineering, the correct and most appropriate choice is '-12e^-4t u(t)' (Option B).
The output of a system whose impulse response is h(t) = e^(-alpha*t) for a delta input is
A)
e^(-alpha*t)
B)
(1 - e^(-alpha*t))
C)
(1 - alpha)e^(-alpha*t)
D)
alpha*e^(-alpha*t)
Based on established principles in Electrical / Electronics Engineering, the correct and most appropriate choice is '(1 - e^(-alpha*t))' (Option B).
The ROC for a finite duration non-causal signal is
A)
Entire Z-plane
B)
Entire Z-plane except Z = 0 and Z = infinity
C)
Entire Z-plane except Z = 0
D)
Entire Z-plane except Z = infinity
Based on established principles in the relevant subject area, the correct and most appropriate choice is 'Entire Z-plane except Z = 0' (Option C).
H(s) is the transfer function H(s) = s / (s^2 - s - 2) (sigma < -1). Then function is
A)
Causal & stable
B)
Causal & unstable
C)
Non-causal & stable
D)
Non-causal & unstable
Based on established principles in the relevant subject area, the correct and most appropriate choice is 'Causal & unstable' (Option B).
A, B, C and D are input bits, and Y is the output bit in the XOR gate circuit of the figure given below. Which of the following statements about the sum S of A, B, C, D and Y is correct?
A)
S=1 only if the sum of A, B, C and D is odd
B)
S is always either zero or odd
C)
S is always either zero or even
D)
S=1 only if the sum of A, B, C and D is even
Based on established principles in Electrical / Electronics Engineering, the correct and most appropriate choice is 'S is always either zero or even' (Option C).
The output Q of a J-K flip-flop is zero. If it change to 1 when a clock pulse is applied, then input J and K are respectively
A)
1 and X
B)
0 and X
C)
X and 0
D)
X and 1
For a J-K flip-flop, when the present output Q = 0 and the next output must become 1 on the clock pulse, the flip-flop must be in the SET condition. In a J-K flip-flop, SET occurs for J = 1 and K = X (don’t care), because K does not affect the transition from 0 to 1 when J is asserted.
Why others are incorrect:
- b (0 and X): J = 0 does not set the flip-flop; it cannot change Q from 0 to 1.
- c (X and 0): K = 0 alone does not force Q to become 1; with J unspecified, this is not the required set condition.
- d (X and 1): K = 1 tends to reset or toggle depending on J, but it does not specifically guarantee a 0 to 1 transition.
Therefore, the correct option is a: 1 and X.
Turn-off time of an SCR is measured from the instant
A)
anode current becomes zero.
B)
anode voltage becomes zero.
C)
anode voltage and anode current become zero at the same time.
D)
gate current becomes zero.
The turn-off time of an SCR is measured from the instant the anode current falls to zero. After the current becomes zero, the SCR does not regain forward blocking ability immediately; it needs a finite time to recover its junctions and remove stored charge. Hence turn-off time is defined starting from the instant anode current becomes zero.
Why the others are incorrect:
- b) Anode voltage becoming zero is not the defining event, because an SCR can turn off only when current is forced below the holding current and then to zero; voltage alone does not define turn-off time.
- c) Anode voltage and anode current becoming zero at the same time is not the standard definition; the key reference is current extinction, not simultaneous zero voltage.
- d) Gate current becoming zero is irrelevant to turn-off time, since the gate signal only triggers turn-on and does not determine the recovery interval after conduction.
A cycloconverter is a
A)
frequency changer from higher to lower frequency with one-stage conversion.
B)
frequency changer from higher to lower frequency with two-stage conversion.
C)
frequency changer from lower to higher frequency with one-stage conversion.
D)
Either (a) or (b)
A cycloconverter is a direct AC-to-AC frequency changer that converts a fixed higher input frequency to a lower output frequency in a single stage, without an intermediate DC link. Hence option (a) is correct. Option (b) is incorrect because two-stage conversion refers to AC-DC-AC conversion, not a cycloconverter. Option (c) is incorrect because cycloconverters do not normally step frequency up; they are used for frequency reduction. Option (d) is incorrect because only (a) is correct, not (b).
In a single-phase full converter, the output voltage during overlap is equal to
A)
zero
B)
source voltage
C)
source voltage minus the inductance drop
D)
none of these
In a single-phase full converter, during the overlap period both incoming and outgoing thyristors conduct simultaneously because of source inductance. The source voltage is then shared in overcoming the inductance, so the load/output voltage is reduced by the inductive drop. Hence, during overlap the output voltage is approximately source voltage minus the inductance drop. Option (c) is correct.
Why others are wrong:
- (a) Zero: output voltage is not zero during overlap; current still flows and the source still contributes voltage.
- (b) Source voltage: this would be true only if there were no overlap (ideal commutation with zero source inductance).
- (d) None of these: incorrect because option (c) correctly describes the overlap condition.
In a full adder, there are
A)
two binary number inputs and two outputs.
B)
three binary digit inputs and two binary outputs.
C)
three binary digit inputs and three binary digit outputs.
D)
two binary digit inputs and one output.
A full adder adds three 1-bit inputs: A, B, and carry-in (Cin). It produces two 1-bit outputs: Sum and carry-out (Cout). Therefore, the correct statement is that a full adder has three binary digit inputs and two binary outputs.
Why the others are wrong:
- a: Incorrect because a full adder does not take only two inputs; it takes three inputs.
- c: Incorrect because a full adder has only two outputs, not three.
- d: Incorrect because two inputs and one output describe a half adder-like idea, not a full adder.
A 4-bit synchronous counter uses flip-flop with propagation delay time of 25 ns each. The maximum possible time required for change of state will be
A)
25 ns
B)
50 ns
C)
75 ns
D)
100 ns
In a synchronous counter, all flip-flops are triggered simultaneously by the same clock edge. Therefore, the change of state does not ripple through the stages one by one as in an asynchronous counter. The maximum time required for the counter output to settle is essentially the propagation delay of a single flip-flop, i.e., 25 ns. Hence, the correct answer is 25 ns.
Why the others are incorrect:
- 50 ns, 75 ns, and 100 ns would apply if the delays of multiple flip-flops were cumulative, which is the case in ripple/asynchronous counters, not synchronous counters.
- Since all 4 flip-flops act in parallel, the number of bits does not multiply the delay in a synchronous counter.
The type of power amplifier which exhibits crossover distortion in its output is
A)
Class A
B)
Class B
C)
Class C
D)
Class D
Class B power amplifiers exhibit crossover distortion because each transistor conducts for only half of the input cycle. Around the zero-crossing point, neither transistor conducts fully, creating a small dead zone and distortion in the output waveform. Class A amplifiers do not suffer from crossover distortion because the device conducts for the entire cycle. Class C amplifiers are highly non-linear and used mainly for RF applications, but crossover distortion is not their defining issue. Class D amplifiers are switching amplifiers; their distortion mechanisms are different and not typically described as crossover distortion.
Which of the following transistor amplifier configurations has the highest power gain?
A)
common base
B)
common collector
C)
common emitter
D)
common source
The common emitter (CE) amplifier has the highest power gain among the BJT transistor configurations because it provides both significant current gain and voltage gain, so their product (power gain) is maximum. In contrast, the common base (CB) configuration has high voltage gain but current gain less than 1, so its power gain is lower than CE. The common collector (CC) configuration has high current gain but voltage gain approximately 1, so its power gain is also lower than CE. The common source option refers to a FET configuration, not a BJT transistor configuration in this context; while common source can have high gain in FETs, for the standard transistor amplifier comparison asked here, the correct answer is common emitter.
The disadvantage of FM over AM is that
A)
noise is very high for high frequency signal.
B)
larger bandwidth is required.
C)
high modulating power is required.
D)
none of these
FM (frequency modulation) has the main disadvantage that it requires a much larger bandwidth than AM for the same information signal. This is because the sidebands in FM extend over a wider frequency range, especially as frequency deviation increases. Hence option (b) is correct.
Why the others are incorrect:
- (a) Noise is not very high in FM; in fact, FM is more immune to noise than AM, especially for amplitude noise.
- (c) FM does not require high modulating power in the same sense as AM; the message signal controls frequency deviation, not carrier amplitude.
- (d) Since (b) is correct, "none of these" is incorrect.
A push-pull amplifier requires
A)
equal input voltages in phase.
B)
equal input voltages with 90o out of phase.
C)
equal input voltages with 180o out of phase.
D)
different input voltages with 90o out of phase.
A push-pull amplifier uses two active devices that operate on opposite halves of the input signal. Therefore, it requires two equal input signals that are 180° out of phase so that one device conducts during the positive half-cycle and the other during the negative half-cycle. This is exactly what option (c) states.
Why the others are wrong:
- (a) Equal input voltages in phase: in-phase signals would make both devices respond the same way, so it would not produce push-pull action.
- (b) Equal input voltages with 90° out of phase: 90° phase difference is not the required condition for push-pull operation.
- (d) Different input voltages with 90° out of phase: both the phase difference and unequal amplitudes are incorrect for a standard push-pull amplifier.
Turn-on time of an SCR can be reduced by using a
A)
rectangular pulse of high amplitude and narrow width
B)
rectangular pulse of low amplitude and wide width
C)
triangular pulse
D)
trapezoidal pulse
An SCR turns on faster when the gate current rises quickly to a sufficiently high value. A rectangular pulse of high amplitude and narrow width provides a large gate current immediately, which reduces the turn-on time and helps the SCR reach conduction rapidly.
Why the others are incorrect:
- b) A low-amplitude, wide pulse gives a weaker gate drive, so turn-on is slower.
- c) A triangular pulse rises gradually, so the gate current builds up more slowly than a rectangular pulse.
- d) A trapezoidal pulse is better than a slowly rising pulse, but it is still not as effective as an immediate high-amplitude rectangular pulse for minimizing turn-on time.
FET is a device which has
A)
high input impedance and is voltage controlled.
B)
high input impedance and is current controlled.
C)
low input impedance and is voltage controlled.
D)
low input impedance and is current controlled.
FET (Field Effect Transistor) is a voltage-controlled device: the gate voltage controls the drain current. It also has very high input impedance because the gate draws negligible current. Therefore, option (a) is correct.
Why others are wrong:
- (b) is incorrect because FET is not current-controlled.
- (c) is incorrect because although FET has high input impedance, it is not low input impedance.
- (d) is incorrect because FET is neither low input impedance nor current-controlled.
During forward blocking state, a thyristor is associated with
A)
large current, low voltage
B)
low current, large voltage
C)
medium current, large voltage
D)
none of these
In the forward blocking state, a thyristor is forward biased but not yet triggered into conduction. Therefore it carries only a small leakage current while sustaining a large forward voltage across it. Hence the correct option is **b: low current, large voltage**. Option **a** is incorrect because large current with low voltage describes the ON-state (forward conduction) of a thyristor. Option **c** is incorrect because the current is not medium; it is very small in the blocking state. Option **d** is incorrect because the correct description is given in option b.
In a single-phase full converter, if á and â are firing and extinction angles respectively, then the load current is
A)
discontinuous if ()
B)
discontinuous if ()
C)
discontinuous if ()
D)
discontinuous if ()
In a single-phase full converter, the load current is continuous only if the conduction interval of each thyristor pair is long enough to overlap the next pair. The conduction interval is measured by (β − α), where α is the firing angle and β is the extinction angle. For continuous current, the current must persist at least up to the next firing instant, which requires (β − α) ≥ π. Therefore, the load current becomes discontinuous when (β − α) < π. Hence option (a) is correct.
Why the others are incorrect:
- (b) (β − α) > π: this corresponds to continuous current, not discontinuous.
- (c) (β − α) = π: this is the boundary case between continuous and discontinuous conduction.
- (d) (β − α) ≥ π: this also indicates continuous conduction (or the limiting case), not discontinuous.
The modulation index of an AM wave is changed from 0 to 1. (The transmitted power is)
A)
unchanged
B)
halved
C)
doubled
D)
increased by 50%
For an AM wave, total transmitted power is P_t = P_c(1 + m^2/2), where P_c is the carrier power and m is the modulation index. When m changes from 0 to 1, the power changes from P_c to P_c(1 + 1/2) = 1.5P_c. Hence the transmitted power increases by 50%. Option (d) is correct.
Why others are wrong: (a) unchanged is incorrect because AM sideband power appears when m > 0, increasing total power. (b) halved is incorrect because power does not decrease; it rises. (c) doubled is incorrect because at m = 1 the total power is only 1.5 times the carrier power, not 2 times.
An SCR can be brought to forward conducting state with gate-circuit open when the applied voltage exceeds
A)
the forward breakdown voltage
B)
reverse breakdown voltage
C)
1.5V
D)
none of these
An SCR with the gate circuit open can still turn ON if the anode-to-cathode forward voltage is raised to the forward breakover (forward breakdown) voltage. At this point, the device enters conduction even without gate triggering. Option (a) is therefore correct.
Option (b) is incorrect because reverse breakdown voltage applies when the SCR is reverse-biased; it does not bring the SCR into forward conduction. Option (c) is incorrect because 1.5 V is not the characteristic breakover voltage of an SCR. Option (d) is incorrect because the correct condition is specifically the forward breakdown voltage.
How many address lines are needed to address each memory location in a 2048 x 4 memory chip?
A)
10
B)
11
C)
12
D)
18
A 2048 × 4 memory chip has 2048 addressable memory locations, each storing 4 bits. The number of address lines required is the number of bits needed to uniquely select 2048 locations: 2^11 = 2048, so 11 address lines are needed. Therefore, option (b) is correct.
Why the others are incorrect: (a) 10 address lines can select only 2^10 = 1024 locations, which is insufficient. (c) 12 address lines would select 2^12 = 4096 locations, more than needed. (d) 18 address lines would select far more locations (2^18), so it is also incorrect.
Time division multiplex
A)
can be used with PCM only
B)
combines five groups into a super group
C)
stacks 24 channels in adjacent frequency slots
D)
interleaves pulses belonging to different transmissions
Time Division Multiplexing (TDM) works by assigning different time slots to different signals and interleaving their pulses in time on the same channel. Hence, option (d) is correct.
Why the others are incorrect:
- (a) "can be used with PCM only" is false. TDM is not limited to PCM; it is a general multiplexing technique, though it is commonly used with digital systems such as PCM.
- (b) "combines five groups into a super group" describes frequency-division multiplexing hierarchy in telephony, not TDM.
- (c) "stacks 24 channels in adjacent frequency slots" also describes FDM, specifically a channel group arrangement, not time division multiplexing.
An amplifier has an open loop gain of 100, an input impedance of 1 kW, and an output impedance of 100W. A feedback network with a feedback factor of 0.99 is connected in a voltage series feedback mode. The new input and output impedances respectively are
A)
10 and 1
B)
10 and 10k
C)
100k and 1
D)
100k and 10
For a voltage-series negative feedback amplifier, the input impedance increases by the factor (1 + A\u03b2) and the output impedance decreases by the same factor.
Given:
- Open-loop gain A = 100
- Feedback factor \u03b2 = 0.99
- Input impedance Ri = 1 k\u03a9
- Output impedance Ro = 100 \u03a9
First compute loop gain:
1 + A\u03b2 = 1 + (100)(0.99) = 1 + 99 = 100
New input impedance:
Rin(new) = Ri(1 + A\u03b2) = 1 k\u03a9 \u00d7 100 = 100 k\u03a9
New output impedance:
Rout(new) = Ro / (1 + A\u03b2) = 100 \u03a9 / 100 = 1 \u03a9
So the correct answer is option d: 100 k\u03a9 and 1 \u03a9.
Why the other options are incorrect:
- a (10 \u03a9 and 1 \u03a9): input impedance is far too small; voltage-series feedback should increase input impedance, not reduce it.
- b (10 \u03a9 and 10 k\u03a9): both values are inconsistent with the feedback effect; output impedance should decrease, not increase.
- c (100 k\u03a9 and 1 \u03a9): this matches the correct input and output impedances, but the option text formatting is garbled; the intended correct pair is 100 k\u03a9 and 1 \u03a9, which corresponds to d in the provided list.
The size of program counter in 8085 microprocessor is
A)
12 bit
B)
16 bit
C)
8 bit
D)
1 byte
The correct answer is **16 bit**. In the 8085 microprocessor, the Program Counter (PC) is a **16-bit register** because it must hold the address of the next instruction in memory, and the 8085 has a 16-bit address bus, allowing it to address up to 64 KB of memory.
Why the other options are incorrect:
- **12 bit**: Too small to address the full memory space of the 8085.
- **8 bit**: An 8-bit register cannot store a full memory address for the 8085.
- **1 byte**: 1 byte = 8 bits, so this is also insufficient for the PC.