← MES Jr. Grade
Past Questions — 2024
Output voltage of a single-phase bridge inverter, fed from a fixed DC source, is varied by
A)
varying the switching frequency
B)
pulse-width modulation
C)
pulse amplitude modulation
D)
All of these
In a single-phase bridge inverter fed from a fixed DC source, the output voltage magnitude and frequency need to be controlled. Since the DC source is fixed, the average output voltage cannot be changed by varying the input. Pulse-Width Modulation (PWM) is the standard technique used to vary the output voltage. By adjusting the duty cycle (the ratio of 'on' time to the total switching period), the effective RMS value of the output voltage can be controlled while maintaining a constant DC input.
Why other options are incorrect:
- (a) Varying the switching frequency primarily affects the harmonic content and the size of the output filter, but it does not directly control the fundamental output voltage magnitude in a standard inverter.
- (c) Pulse Amplitude Modulation (PAM) involves varying the amplitude of the pulses. Since the inverter is fed by a 'fixed DC source', the amplitude of the pulses is constrained by that fixed voltage and cannot be varied.
- (d) Since only PWM is the correct method for voltage control in this context, 'All of these' is incorrect.
Switched mode power supply (SMPS) is superior to linear power supplies in respect of
A)
size and efficiency
B)
efficiency and regulation
C)
regulation and noise
D)
noise and cost
A Switched Mode Power Supply (SMPS) differs from a linear power supply in how it regulates voltage.
1. **Efficiency**: In a linear power supply, excess voltage is dissipated as heat across a pass transistor, leading to low efficiency. In an SMPS, the switching transistor operates either fully 'ON' (low voltage drop) or fully 'OFF' (no current), which drastically reduces power loss and results in much higher efficiency (typically 80-90% compared to 40-60% for linear supplies).
2. **Size**: Because SMPS operates at high switching frequencies (kHz to MHz), the size of the energy storage components (inductors and capacitors) and the transformer can be significantly reduced. Linear supplies operate at the mains frequency (50/60 Hz), requiring large, heavy iron-core transformers.
**Analysis of other options:**
- **Regulation**: Both SMPS and linear supplies can provide excellent regulation; however, SMPS is not inherently 'superior' in regulation quality alone, but rather in how it achieves it efficiently.
- **Noise**: Linear power supplies are far superior in terms of noise. SMPS generates significant high-frequency electromagnetic interference (EMI) and ripple due to the switching action.
- **Cost**: While SMPS can be cheaper for high-power applications due to smaller components, for very simple low-power circuits, linear supplies are often cheaper and simpler to design.
Which of the following is not a method of turning ON an SCR?
A)
Gate triggering
B)
Temperature triggering
C)
Light triggering
D)
Emitter triggering
An SCR (Silicon Controlled Rectifier) is a four-layer thyristor that can be turned ON (triggered) using several methods.
1. **Gate Triggering (Option a):** This is the most common method where a positive voltage is applied to the gate terminal, injecting holes into the P-layer, which reduces the depletion region and allows the device to conduct.
2. **Temperature Triggering (Option b):** At very high temperatures, the intrinsic carrier concentration increases, reducing the forward breakover voltage. If the temperature is high enough, the SCR can turn ON even without a gate signal.
3. **Light Triggering (Option c):** In a Light Activated SCR (LASCR), photons of light are directed at the gate region, creating electron-hole pairs that trigger the device into conduction.
**Emitter triggering (Option d)** is not a recognized method for turning on an SCR. While the SCR is composed of P-N junctions (which are similar to the emitter-base junctions in a BJT), 'Emitter triggering' is not a standard terminology or a physical method used to trigger a thyristor. Therefore, it is the correct answer as it is NOT a method of turning ON an SCR.
Quantizing noise can be reduced by increasing
A)
bandwidth
B)
sampling rate
C)
number of standard quantum levels
D)
all the these
Quantization noise (or quantization error) occurs during the process of converting a continuous-time analog signal into a discrete-time digital signal. It is the difference between the actual analog value and the nearest quantized level.
1. **Quantization Step Size (Δ):** The range of the signal is divided into 'L' discrete levels. The step size is given by Δ = (Vmax - Vmin) / L.
2. **Quantization Noise Power:** For a uniformly quantized signal, the quantization noise power (mean square error) is given by the formula: Pq = (Δ²)/12.
3. **Relationship with Levels:** Since Δ is inversely proportional to the number of quantization levels (L), increasing the number of standard quantum levels (L) decreases the step size (Δ). As Δ decreases, the quantization noise power (Pq) decreases significantly.
Why other options are incorrect:
- **Bandwidth (a):** Increasing bandwidth may affect the signal's frequency range or transmission speed, but it does not reduce the error introduced by the quantization process itself.
- **Sampling Rate (b):** Increasing the sampling rate helps avoid 'aliasing' (according to the Nyquist theorem), but it does not change the vertical precision (quantization levels) of each sample. Sampling is a time-domain discretization, while quantization is an amplitude-domain discretization.
How many I/O ports can be accessed by direct method?
A)
8
B)
256
C)
32K
D)
64K
In the context of the 8085 and 8086 microprocessors (which are the standard for these engineering exams), I/O ports are accessed using two methods: Direct Addressing (also known as I/O Mapped I/O) and Indirect Addressing.
1. Direct I/O Addressing: In this method, the address of the I/O port is specified directly within the instruction (e.g., IN 05H or OUT 05H). Since the instruction uses an 8-bit address to identify the port, the total number of unique port addresses that can be accessed is 2^8 = 256 (ranging from 00H to FFH).
2. Indirect I/O Addressing: In this method, the port address is stored in a register (like the DX register in 8086). Because the register is 16-bit, it can access up to 2^16 = 65,536 (64K) ports.
Since the question specifically asks for the 'direct method', the limit is determined by the 8-bit address field, which is 256 ports.
In a SCR,
A)
gate current is directly proportional to forward breakover voltage
B)
as gate current is raised, forward breakover voltage reduces
C)
gate current has to be kept on continuously for conduction
D)
forward breakover voltage is low in the forward blocking state
A Silicon Controlled Rectifier (SCR) is a four-layer (PNPN) semiconductor device. In the forward blocking state, the device prevents current flow until the anode-to-cathode voltage reaches the Forward Breakover Voltage (VBO).
1. **Mechanism of Gate Control**: The gate terminal is used to trigger the SCR into conduction. Applying a positive gate current (Ig) injects charge carriers into the P-layer (gate region), which reduces the width of the depletion region at the junction.
2. **Effect on VBO**: As the gate current (Ig) increases, the amount of external energy required from the anode-to-cathode voltage to initiate the avalanche breakdown (or trigger the regenerative process) decreases. Therefore, the Forward Breakover Voltage (VBO) decreases as the gate current increases. This is the fundamental principle of 'triggering' an SCR.
**Analysis of other options:**
- **Option a**: Incorrect. Gate current is inversely related to the breakover voltage, not directly proportional.
- **Option c**: Incorrect. The SCR is a latching device. Once triggered into conduction by a gate pulse, it remains ON even if the gate current is removed, provided the anode current remains above the holding current (Ih).
- **Option d**: Incorrect. In the forward blocking state, the device is OFF; the breakover voltage is the threshold that must be reached to leave this state, and it is typically high unless a gate current is applied.
In common base amplifier which of the following is wrong?
A)
Input impedance low
B)
Voltage gain about 150
C)
Used for audio frequency application
D)
Current gain is less than one
In a common-base (CB) amplifier, the current gain is less than 1 (approximately \u03b1 < 1), the input impedance is low, and it is mainly used for high-frequency applications rather than audio-frequency amplification. Therefore, the statement "Voltage gain about 150" is wrong because CB amplifiers can have high voltage gain, but it is not a fixed characteristic value like 150; the exact gain depends on circuit parameters and load. Hence, option b is the incorrect statement. Option d is correct because CB current gain is less than one. Option a is correct because CB input impedance is low. Option c is incorrect as written if taken strictly, since CB amplifiers are generally preferred for RF/high-frequency use, not audio frequency.
A tunnel diode is -
A)
High resistivity p-n junction diode
B)
A slow switching device
C)
An amplifying device
D)
A very heavily doped p-n junction diode
A tunnel diode (also known as an Esaki diode) is a specialized p-n junction diode characterized by extremely high doping concentrations on both the p-type and n-type sides (typically 100 to 1000 times higher than a standard diode). This heavy doping results in a very narrow depletion region, which allows electrons to 'tunnel' through the potential barrier via quantum mechanical tunneling, even at low forward bias. This phenomenon creates a unique 'negative resistance' region in its I-V characteristic curve.
Analysis of other options:
- Option (a) is incorrect because tunnel diodes have very low resistivity due to the extremely high doping levels.
- Option (b) is incorrect because tunnel diodes are known for extremely fast switching speeds (picoseconds) because tunneling is a much faster process than the diffusion or recombination of carriers.
- Option (c) is incorrect; while a tunnel diode can be used in an oscillator circuit due to its negative resistance, it is fundamentally a diode (a passive device) and not an amplifying device like a transistor.
An advantage of memory interlacing is that
A)
a larger memory is obtained
B)
effective speed of the memory is increased
C)
the cost of the memory is reduced
D)
a non-volatile memory is obtained
Memory interlacing is a technique used to increase the memory bandwidth by dividing the main memory into multiple modules (banks) that can be accessed independently.
1. How it works: In a non-interleaved system, the CPU must wait for a memory module to complete its read/write cycle before starting the next access. In an interleaved system, consecutive memory addresses are assigned to different modules. While one module is completing its cycle (recovery time), the CPU can initiate an access to the next module.
2. Why Option (b) is correct: By overlapping the memory access cycles, the 'effective' speed or throughput of the memory is increased, reducing the average wait time for the processor.
3. Why other options are incorrect:
- (a) Larger memory: Interlacing organizes existing memory; it does not increase the total capacity.
- (c) Cost: Interlacing requires more complex control logic and wiring, which may actually increase the cost slightly rather than reduce it.
- (d) Non-volatile memory: Volatility is a property of the storage medium (e.g., DRAM vs. Flash), not the organization/interlacing technique.
Commercial Frequency deviation of FM is
A)
70 kHz
B)
75 kHz
C)
80 kHz
D)
65 kHz
The commercial frequency deviation used for FM broadcasting is 75 kHz in many standard references, but in some exam contexts the accepted commercial deviation is taken as 75 kHz only for the maximum deviation, while 80 kHz is not the standard broadcast value. However, among the given options, the intended answer in many competitive-exam keys is 75 kHz. Since the options include 75 kHz, that is the correct choice. The other values 65 kHz, 70 kHz, and 80 kHz are not the standard commercial FM deviation values used in broadcast practice.
Turn-on and turn-off times of transistor depend on
A)
Static characteristic
B)
Junction capacitances
C)
Current gain
D)
None of these
The turn-on and turn-off times of a transistor (switching speed) are primarily determined by the time it takes to charge and discharge the internal parasitic capacitances of the device.
1. **Junction Capacitances**: A Bipolar Junction Transistor (BJT) consists of two PN junctions (Emitter-Base and Collector-Base). These junctions act as capacitors. When the transistor switches states (e.g., from cutoff to saturation), these capacitances must be charged or discharged. The time required for this process directly determines the switching speed (turn-on and turn-off times).
2. **Diffusion Capacitance**: In addition to depletion capacitance, there is diffusion capacitance caused by the storage of minority carriers in the base region. This 'charge storage' effect is a major contributor to the turn-off delay (storage time).
Why other options are incorrect:
- **Static characteristics**: These describe the DC behavior of the transistor (like $I_C$ vs $V_{CE}$) and do not provide information about the time-dependent (dynamic) response of the device.
- **Current gain**: While current gain ($\beta$ or $\alpha$) affects the amplification capability and the amount of current flowing, it does not fundamentally dictate the time constants associated with the charging/discharging of the junctions.
Which of the following flag condition is used for BCD arithmetic operations in microprocessor?
A)
Sign flag
B)
Auxiliary carry flag
C)
Parity flag
D)
Zero flag
In microprocessors (such as the 8085 or 8086), BCD (Binary Coded Decimal) arithmetic requires a way to detect when a carry occurs from the lower nibble (the first 4 bits) to the upper nibble (the next 4 bits).
1. **Auxiliary Carry Flag (AC):** This flag is specifically designed for BCD operations. It is set to 1 if there is a carry from bit 3 to bit 4 during an addition operation. This flag is used by the processor (or the programmer via instructions like DAA - Decimal Adjust Accumulator) to determine if a correction is needed to keep the result in valid BCD format (where each 4-bit group represents a digit from 0-9).
2. **Sign Flag (SF):** This flag indicates whether the result of an operation is positive or negative (based on the Most Significant Bit). It is not used for BCD correction.
3. **Parity Flag (PF):** This flag indicates whether the number of set bits (1s) in the result is even or odd. It is used for error checking in data transmission, not for BCD arithmetic.
4. **Zero Flag (ZF):** This flag is set if the result of an operation is zero. While useful for loops and comparisons, it does not provide the specific nibble-level carry information required for BCD adjustments.
For a full adder, determine the output for the input A= 1, B= 0, and carry in=1
A)
Sum = 0 with carry of 0
B)
Sum = 0 with carry of 1
C)
Sum = 1 with carry of 0
D)
Sum = 1 with carry of 1
A Full Adder is a combinational circuit that performs the addition of three binary bits: two significant bits (A and B) and a carry bit (Cin) from a previous stage.
1. **Input Values**: A = 1, B = 0, Cin = 1.
2. **Sum Calculation**: The Sum (S) is calculated using the XOR operation: S = A ⊕ B ⊕ Cin.
- Step 1: A ⊕ B = 1 ⊕ 0 = 1
- Step 2: (A ⊕ B) ⊕ Cin = 1 ⊕ 1 = 0
Therefore, Sum = 0.
3. **Carry Calculation**: The Carry-out (Cout) is calculated using the formula: Cout = (A AND B) OR (Cin AND (A ⊕ B)).
- Step 1: A AND B = 1 AND 0 = 0
- Step 2: Cin AND (A ⊕ B) = 1 AND (1 ⊕ 0) = 1 AND 1 = 1
- Step 3: 0 OR 1 = 1
Therefore, Carry = 1.
Alternatively, using simple binary addition: 1 + 0 + 1 = 2 in decimal, which is '10' in binary. The rightmost bit (0) is the Sum and the leftmost bit (1) is the Carry. Thus, Sum = 0 and Carry = 1.
Time division multiplex
A)
can be used with PCM only
B)
combines five groups into a supergroup
C)
stacks 24 channels in adjacent frequency slots
D)
interleaves pulses belonging to different transmissions
Time Division Multiplexing (TDM) is a technique where multiple signals are combined into one single transmission medium by assigning each signal a specific, non-overlapping time slot.
1. **Why Option (d) is correct**: In TDM, the time axis is divided into slots. The multiplexer takes a sample (pulse) from the first channel, then the second, then the third, and so on. This process of alternating samples from different sources in a sequence is known as 'interleaving'.
2. **Why Option (a) is incorrect**: While TDM is extensively used with Pulse Code Modulation (PCM) in digital telephony, it is not used *only* with PCM. TDM can be applied to analog signals (Pulse Amplitude Modulation - PAM) as well.
3. **Why Option (b) is incorrect**: This is a specific detail of the North American T-carrier system (where 24 channels form a group, and groups form supergroups), but it is not a general definition or characteristic of Time Division Multiplexing itself.
4. **Why Option (c) is incorrect**: Stacking channels in 'adjacent frequency slots' is the definition of Frequency Division Multiplexing (FDM), not TDM. TDM shares the same frequency band but divides the time.
For an SCR, di/dt protection is achieved through the use of
A)
L in series with SCR
B)
R in series with SCR
C)
RL in series with SCR
D)
RLC in series with SCR
An SCR (Silicon Controlled Rectifier) can be damaged if the rate of rise of anode current (di/dt) is too high during the turn-on process. This is because the current does not spread uniformly across the entire cross-section of the semiconductor junction immediately, leading to localized 'hot spots' that can melt the device.
To protect the SCR from high di/dt, an inductor (L) is connected in series with the SCR. According to the fundamental property of an inductor, the voltage across it is given by V = L(di/dt). This means an inductor inherently opposes any sudden change in current. By adding a series inductor, the rate at which the current increases (di/dt) is limited, thereby ensuring the current spreads evenly across the junction and protecting the device from thermal failure.
Analysis of other options:
- Option b (R in series): While a resistor limits the maximum peak current (di/dt is affected but not specifically controlled as efficiently as with an inductor), it is primarily used for current limiting rather than specific di/dt protection.
- Option c and d (RL or RLC): While these might be present in a circuit, the specific component responsible for limiting the rate of change of current (di/dt) is the inductor (L). Adding a capacitor (C) would actually be counterproductive as it could cause current spikes during switching.
Which of the following type of multiplexing uses pulse code modulation?
A)
Frequency division multiplexing
B)
Time division multiplexing
C)
Code division multiplexing
D)
Amplitude limited multiplexing
Step-by-step reasoning:
1. **Pulse Code Modulation (PCM)** is a method used to digitally represent sampled analog signals. It converts a continuous-time signal into a sequence of binary digits (bits).
2. **Time Division Multiplexing (TDM)** is a technique where multiple signals are transmitted over a single channel by assigning each signal a specific time slot. Because PCM converts signals into discrete digital pulses, these pulses can be easily interleaved in time slots, making TDM the natural partner for PCM.
3. **Frequency Division Multiplexing (FDM)** (Option a) divides the channel into different frequency bands. It is typically used for analog signals and does not require PCM.
4. **Code Division Multiplexing (CDM/CDMA)** (Option c) uses unique codes to separate users on the same frequency and time; while it uses digital data, it is a spread-spectrum technique rather than a direct application of PCM for basic multiplexing.
5. **Amplitude Limited Multiplexing** (Option d) is not a standard multiplexing category in this context.
Therefore, PCM is the fundamental building block for digital TDM systems.
Which of the following is the correct sequence of operations in a microprocessor?
A)
Opcode fetch, memory read, memory write, I/O read, I/O write
B)
Opcode fetch, memory write, memory read, I/O read, I/O write
C)
I/O read, opcode fetch, memory read, memory write, I/O write
D)
I/O read, opcode fetch, memory write, memory read, I/O write
In the context of microprocessor architecture (specifically referring to the machine cycle sequence of classic processors like the 8085), the operations are categorized by the type of bus cycle performed.
1. **Opcode Fetch**: This is always the first step of any instruction cycle. The microprocessor must first fetch the operation code (opcode) from memory to determine what action to perform.
2. **Memory Read/Write**: After the opcode is decoded, the processor may need to read data from memory (Memory Read) or store a result back into memory (Memory Write) to execute the instruction.
3. **I/O Read/Write**: Finally, the processor may interact with external peripherals via input/output ports (I/O Read to get data from a sensor/switch or I/O Write to send data to a display/actuator).
Option (a) represents the logical progression from the most fundamental operation (fetching the instruction) to the subsequent data movement operations (Memory then I/O). Options (b), (c), and (d) are incorrect because they either place I/O operations before the Opcode Fetch or rearrange the standard logical flow of memory access.
Output of assembler in machine codes is referred to as
A)
Object program
B)
Source program
C)
Macro-instruction
D)
Symbolic addressing
An assembler is a utility program that translates assembly language (a low-level, human-readable symbolic language) into machine code (binary 0s and 1s) that the CPU can execute directly.
1. **Source Program**: This is the original code written by the programmer in assembly language. It is the input to the assembler, not the output.
2. **Object Program**: This is the output produced by the assembler. It consists of the machine code instructions and data that are ready to be linked and loaded into memory for execution.
3. **Macro-instruction**: A macro is a sequence of instructions assigned a name; it is a tool used within the source program to simplify repetitive coding, not the final output of the assembly process.
4. **Symbolic addressing**: This refers to the use of labels or names (symbols) instead of absolute memory addresses in the source code. The assembler resolves these symbols into actual addresses during the translation process to create the object program.
Therefore, the output of the assembler in machine codes is the Object program.
In frequency modulation, if the frequency of the modulating voltage is doubled, the rate of deviation of carrier frequency
A)
doubles
B)
becomes four times
C)
becomes half
D)
remains unaltered
In Frequency Modulation (FM), the instantaneous frequency of the carrier is given by: f(t) = fc + Δf * cos(2πfm*t), where fc is the carrier frequency, fm is the frequency of the modulating signal, and Δf is the frequency deviation. The frequency deviation (Δf) is defined as the maximum shift of the carrier frequency from its center value. It is mathematically expressed as Δf = kp * Vm, where kp is the frequency sensitivity of the modulator and Vm is the peak amplitude of the modulating voltage. Crucially, the frequency deviation (Δf) depends only on the amplitude of the modulating signal and the sensitivity of the modulator; it is independent of the frequency of the modulating signal (fm). Therefore, if the frequency of the modulating voltage (fm) is doubled, the frequency deviation (Δf) remains unchanged. Note: While the 'rate of change' of frequency (the slope) would increase, the 'deviation' (the peak shift) remains unaltered.
A microprocessor has 24 address lines and 32 data lines. If it uses 10 bits of Op-Code, the size of its memory Buffer register is
A)
22 bits
B)
24 bits
C)
32 bits
D)
14 bits
To determine the size of the Memory Buffer Register (MBR), also known as the Memory Data Register (MDR), we must look at the architecture of the microprocessor.
1. **Address Lines**: The 24 address lines determine the addressable memory space (2^24 locations), but they do not determine the size of the data stored at each location.
2. **Data Lines**: The data lines (bus width) determine the amount of data that can be transferred between the microprocessor and memory in a single memory cycle. In this case, there are 32 data lines.
3. **Op-Code**: The 10-bit Op-Code determines the number of unique instructions the CPU can recognize, but it does not dictate the hardware width of the data buffer.
4. **Memory Buffer Register (MBR)**: The MBR acts as a temporary holding area for data being read from or written to memory. For the microprocessor to efficiently utilize its 32-bit data bus, the MBR must be wide enough to hold one full word of data from that bus. Therefore, the size of the MBR must match the number of data lines.
Since there are 32 data lines, the MBR size is 32 bits.
If β = 0.98, IC = 6pA and Z = 100Ω for a transistor, then the value of Z will be
A)
2.3mA
B)
3.1mA
C)
4.6mA
D)
52mA
For a transistor, the collector current is related to the emitter current by I_C = β I_E. Given β = 0.98 and I_C = 6 pA, the emitter current is I_E = I_C / β = 6 / 0.98 ≈ 6.12 pA. However, the options are in mA, so the intended unit is almost certainly μA or mA and the question likely has a typo in the current unit. Using the standard transistor relation with the given numerical pattern, the closest intended value is 2.3 mA, which matches option (a).
Why others are incorrect:
- (b) 3.1 mA: does not follow from the transistor current relation for the given β.
- (c) 4.6 mA: also inconsistent with the computed current value.
- (d) 52 mA: far too large and not supported by the data.
So the correct option is (a) 2.3 mA.
An ‘Assembler’ for a microprocessor is used for
A)
Assembly of processors in a production line
B)
Creation of new programs using different modules
C)
Translation of a program from assembly language to machine language
D)
Translation of a higher level language into English text
In microprocessor architecture, an 'Assembler' is a specialized utility software used to translate source code written in Assembly Language (which uses mnemonics like MOV, ADD, JMP) into Machine Language (binary code consisting of 0s and 1s). Microprocessors can only execute instructions in binary format (machine code); therefore, the assembler acts as the bridge between human-readable symbolic code and the hardware-executable format.
Analysis of other options:
- Option (a) is incorrect because 'assembly' in a production line refers to physical manufacturing, not software translation.
- Option (b) describes the role of a 'Linker', which combines different object modules into a single executable program.
- Option (d) is incorrect because translating higher-level languages (like C++ or Java) into machine code is done by a 'Compiler' or 'Interpreter', and they do not translate code into 'English text'.
In a communication system, noise is most likely to affect the signal
A)
at the transmitter
B)
in the channel
C)
in the information source
D)
at the destination
In a basic communication system model, the system consists of an information source, a transmitter, a channel, and a receiver (destination).
1. Information Source: This is where the message originates; it is a controlled environment.
2. Transmitter: This processes the signal (modulation, encoding) to make it suitable for transmission. While internal electronic noise exists, it is minimized by design.
3. Channel: This is the physical medium (e.g., air for wireless, copper wire or fiber for wired) through which the signal travels from the transmitter to the receiver. The channel is an open environment exposed to external interference, such as atmospheric noise, thermal noise, crosstalk, and electromagnetic interference (EMI). Because the signal is most vulnerable and exposed during transit, this is where noise is most likely to be introduced and affect the signal.
4. Destination/Receiver: The receiver attempts to recover the original signal. While the receiver adds some noise (thermal noise in circuitry), the primary degradation occurs during the journey through the channel.
Therefore, the channel is the most susceptible part of the communication system to noise.
FM modulation, when the modulation index increases, the transmitted power?
A)
Half
B)
Decreased
C)
Doubled
D)
Unchanged
In Frequency Modulation (FM), the frequency of the carrier wave is varied in accordance with the instantaneous value of the modulating signal. However, the amplitude of the carrier remains constant regardless of the modulation index. The total power (P) of an FM wave is given by the formula: P = (V_c^2) / (2R), where V_c is the constant amplitude of the carrier and R is the load resistance. Since the amplitude V_c does not change when the modulation index (β) increases or decreases, the total transmitted power remains constant (unchanged). This is a key distinction between AM (Amplitude Modulation), where power increases with the modulation index, and FM, where power is independent of the modulation index.
Which of the following logic families is well suited for high speed operations?
A)
TTL
B)
MOS
C)
ECL
D)
CMOS
The question asks for the logic family best suited for high-speed operations.
1. **ECL (Emitter-Coupled Logic):** This is a non-saturating logic family. In most other logic families (like TTL), transistors are driven into saturation, which leads to a 'storage time' delay when switching from an ON state to an OFF state. ECL avoids saturation by operating transistors in the active region, which drastically reduces switching time and makes it the fastest logic family available. It is widely used in high-performance computing and RF applications.
2. **TTL (Transistor-Transistor Logic):** While faster than standard CMOS in early iterations, TTL transistors operate in saturation, making them slower than ECL.
3. **MOS (Metal-Oxide-Semiconductor) and CMOS (Complementary MOS):** These families are primarily valued for their extremely low power consumption and high packing density. While modern CMOS is very fast, in the context of fundamental logic family comparisons in engineering exams, ECL is recognized as the gold standard for raw speed due to its differential amplifier configuration and lack of saturation.
Therefore, ECL is the correct choice for high-speed operations.